An interactive companion for CPU designers
The RISC-V Instruction Set Manual
Volumes I (Unprivileged) & II (Privileged) rebuilt as an interactive textbook, focused on one goal: giving a hardware designer the detailed mechanisms needed to build a RISC-V CPU that boots Linux.
Source: The RISC-V Instruction Set Manual, Version 20260120 (Official Release) — RISC-V International.
Every page answers one question: what does the hardware do?
This isn't the spec re-typeset. Each section carries a Hardware Designer Notes callout (what a hart MUST implement vs MAY trap-and-emulate, the WARL/WLRL corner cases, the gate count), an interactive widget where it helps — CSR field maps, instruction encodings, litmus tests, the vsetvli strip-mine loop — and a check-yourself quiz. A Linux boot tag on every page tells you whether it is on the critical path to a booting kernel.
Part I — The Linux-Boot Core ISA
The unprivileged instruction set a Linux-capable RV64GC hart implements: the base integer ISA, M/A/F/D/C, CSR access, counters, and the RVWMO memory model.
17 chapters · 37/37 sections
Part II — Privileged Architecture
Everything Volume II defines: machine and supervisor modes, traps, CSRs, virtual memory (Sv39/48/57), PMP, and the hypervisor extension.
21 chapters · 39/39 sections
Part III — Beyond the Core: Other Extensions
The rest of Volume I at the same depth — vector, bit-manipulation, crypto, and the other ratified extensions — kept separate from the Linux-boot core.
26 chapters · 76/76 sections
Browse by chapter in the sidebar, walk the build order on the roadmap, or look up a term in the glossary.