Vector FP mirrors the scalar F/D semantics lane-wise: IEEE 754-2008, dynamic frm rounding, and fflags set only by active elements — masked-off lanes are architecturally silent.
| Semantics & notes | |
|---|---|
| vfadd / vfsub / vfrsub.vf | Add, subtract, and REVERSE subtract (f[rs1] − vs2[i]) — the reverse form exists only for .vf, where operand roles can’t be swapped in assembly. |
| vfwadd / vfwsub (.vv/.vf and .wv/.wf) | 2·SEW results; the .w* forms take an ALREADY-wide first source (2·SEW += SEW accumulation without re-narrowing). |
| vfmul / vfdiv / vfrdiv.vf | Multiply, divide, and scalar÷vector reverse divide. |
| vfwmul | Full-precision widening multiply into a 2·LMUL group. |
| vfmacc / vfnmacc / vfmsac / vfnmsac | Fused multiply-add overwriting the ADDEND: ±(vs1·vs2) ± vd, all four sign patterns, single rounding. |
| vfmadd / vfnmadd / vfmsub / vfnmsub | The multiplicand-overwriting forms: ±(vs1·vd) ± vs2. |
| vfwmacc / vfwnmacc / vfwmsac / vfwnmsac | Widening FMAs: 2·SEW accumulator ± SEW×SEW product — the FP dot-product engine (and the pattern BF16’s vfwmaccbf16 borrows). |
| vfsqrt.v | Element-wise square root (unary, from the VFUNARY encoding space). |
| vfrsqrt7.v | Reciprocal square-root ESTIMATE to ~7 bits — table-based seed for Newton-Raphson iteration; exact table specified so all implementations agree bit-for-bit. |
The estimate instructions deserve a note: vfrsqrt7 (and vfrec7,
next page) return ~7-bit-accurate seeds from architecturally
specified lookup tables — bit-exact across implementations, so
Newton-Raphson refinement converges identically everywhere. That’s
the difference from other ISAs’ loosely-specified estimates that
break cross-platform reproducibility.
Hardware Designer Notes
The FMA lane is the area king of the vector unit — budget it first. Everything else on this page shares its multiplier and adder. If you support Zvfh (vector half), the widening FMA path doubles as the fp16→fp32 ML kernel, which is where the silicon earns rent.
Minimal Linux-boot hart MUST
- Suppress fflags updates from inactive/tail lanes — predication must gate the flag tree, not just writeback
- Implement the specified vfrsqrt7 lookup table exactly (the spec defines every entry) — approximate tables are non-conformant
- Check frm validity for EVERY vector FP instruction, including non-rounding ones and vl=0 cases (reserved otherwise)
MAY simplify / trap-and-emulate
- Build lanes as replicated scalar FMA units — the semantics are deliberately identical; SEW gating and NaN-boxing at the .vf scalar port are the only vector-isms
- Iterate vfdiv/vfsqrt on a shared non-pipelined unit — throughput kernels avoid them; dot products (vfwmacc) are what must stream
Check yourself — vector FP arithmetic
1.A masked-off element would have produced an invalid-operation exception. What happens to fflags?
2.Why do vfrsub.vf and vfrdiv.vf exist, but no .vv reverse forms?
3.What do the .wv forms of vfwadd give you that the plain .vv widening forms don't?
4.Why does the vector ISA lack non-destructive FMAs when two scalar-FMA rounding-mode encodings were available to encode them?