Two of the most-thumbed reference tables in the whole manual live here: how other architectures’ code lands on RISC-V, and which shortcuts a conservative implementation may take.
A.5 The porting tables
| Source op | RVWMO mapping | |
|---|---|---|
| x86/TSO load | mov (load) | l{b|h|w|d}; fence r,rw |
| x86/TSO store | mov (store) | fence rw,w; s{b|h|w|d} |
| x86 LOCK-prefix RMW | lock add … | amo<op>.aqrl, or lr.aq; <op>; sc.aqrl; bnez |
| Power lwsync / sync | fence.tso / fence rw,rw | |
| Power isync · ARM isb | fence.i; fence r,r | |
| ARM load-acquire | ldar | fence rw,rw; ld; fence r,rw |
| ARM store-release | stlr | fence rw,w; st |
| ARM exclusives | ldxr/stxr (+acq/rel) | lr / sc (lr.aqrl for acquire-exclusive, sc.rl for release-exclusive) |
| ARM dmb / dmb.ld / dmb.st | fence rw,rw / fence r,rw / fence w,w |
| RVWMO mapping | |
|---|---|
| smp_mb() / smp_rmb() / smp_wmb() | fence rw,rw / fence r,r / fence w,w |
| mb() / rmb() / wmb() (I/O-inclusive) | fence iorw,iorw / fence ri,ri / fence wo,wo |
| smp_load_acquire() | l…; fence r,rw |
| smp_store_release() | fence.tso; s… |
| Linux atomic <op> (fully ordered) | amo<op>.aqrl, or lr.aq; <op>; sc.aqrl loop |
| C11 atomic_load(seq_cst) | fence rw,rw; l…; fence r,rw |
| C11 atomic_store(seq_cst) | fence rw,w; s… |
| C11 atomic_<op>(seq_cst) via LR/SC | lr.aqrl; <op>; sc.rl; bnez |
Soundness precondition: the region carries PMAs main memory, coherent,
AMOArithmetic, RsrvEventual. AMO emulation on LR/SC-only hardware maps
AMOs to lr.aq; <op>; sc.aqrl so all AMO-originated orderings survive.
A.6 The conservative-implementation menu
RVWMO never requires weakness. The appendix explicitly blesses, among
others: treating every fence as RW,RW (or IORW,IORW); emulating
aq/rl with fences; enforcing full same-address load-load ordering
(skipping the fri-rfi/RSW subtleties); forbidding all forwarding from
stores to AMOs/LRs and from AMOs/SCs to loads; or simply implementing
TSO everywhere (Ztso) with fully ordered atomics. RVTSO cores may
additionally ignore all fences lacking PW+SR and all PPO rules but 4–7.
Expectations, both directions: software uses rules 1 and 4–8 routinely, experts use 9–11; rules 2–3 and 12–13 exist for microarchitecture and formal modeling. Hardware finds rules 1, 3–6 familiar; rule 2 is the one flagged “worth double checking carefully.” And syntactic dependencies must never be optimized away in the ordering domain.
Two aggressive-optimization warnings: silent stores (and value-unchanged AMOs) are still architecturally stores — eliding them collides with RSW reasoning; and write subsumption write subsumption Eliding the earlier of two back-to-back same-address writes. Legal ONLY when model-invisible: subsuming a store that carries a dependency (Table 92) would break a required ordering chain - forbidden. Silent stores and value-unchanged AMOs are still architecturally stores. defined in ch. I·A — open in glossary is legal only when invisible — Table 92 shows a subsumed store whose data dependency was load-bearing, making the elision a model violation.
Hardware Designer Notes
For the Linux-boot mission, this page doubles as your software
compatibility contract: the kernel is compiled with exactly the Table 89
mappings, so your core must make THOSE sequences correct and reasonably
fast — fence r,rw, fence.tso, amo.aqrl are the hot ordering ops on
every syscall path. The conservative menu is how you get correct first;
the fence-granularity optimizations are how you get fast later.
Minimal Linux-boot hart MUST
- Preserve syntactic dependencies in the ordering domain even when value-optimizing (move elimination, zero detection)
- Audit write-combining/subsumption against dependency chains (Table 92)
- Treat silent stores as stores
MAY simplify / trap-and-emulate
- Take the entire conservative menu for v1: full fences, aq/rl-as-fences, no atomic forwarding, strict same-address ordering
- Go Ztso wholesale and ignore PW/SR-less fences
Check yourself — porting maps & implementation menu
1.How does an x86 (TSO) plain load map onto RVWMO?
2.Why does Linux's smp_store_release() map to fence.tso; store rather than fence rw,w; store?
3.Which PMAs must the platform provide for the C11 mappings to be sound on a memory region?
4.Your v1 core wants maximum simplicity. Which shortcuts does the appendix explicitly bless?
5.When is eliding the earlier of two back-to-back same-address stores (write subsumption) illegal?