When a trap fires, three registers tell the handler everything:
mcause (what), mepc (where — previous page), mtval (the details).
This page also covers menvcfg, M-mode’s feature-gate panel.
3.1.15 mcause and Table 16
mcause mcause Interrupt bit + WLRL code. Interrupts: 1/3 SSI/MSI, 5/7 STI/MTI, 9/11 SEI/MEI, 13 LCOFI. Exceptions: 0 IAM, 1 IAF, 2 illegal, 3 breakpoint, 4/6 load/store misaligned, 5/7 load/store access fault, 8/9/11 ecall U/S/M, 12/13/15 page faults, 16 double trap, 18 software check, 19 hardware error. defined in ch. II·3 — open in glossary = Interrupt bit (MSB) + WLRL exception code. One sign-branch separates interrupts; a shift scales the code into a dispatch table.
| Interrupts (MSB=1) | Exceptions (MSB=0) | |
|---|---|---|
| 0 | Reserved | Instruction address misaligned |
| 1 | Supervisor software (SSI) | Instruction access fault |
| 2 | Reserved | Illegal instruction |
| 3 | Machine software (MSI) | Breakpoint (EBREAK, triggers) |
| 4 / 5 | Reserved / Supervisor timer (STI) | Load address misaligned / Load access fault |
| 6 / 7 | Reserved / Machine timer (MTI) | Store-AMO misaligned / Store-AMO access fault |
| 8 / 9 / 11 | Reserved / Supervisor external (SEI) / Machine external (MEI) | ECALL from U / S / M |
| 12 / 13 / 15 | 12 reserved / 13 counter-overflow (LCOFI) | Instruction / load / store-AMO page fault |
| 16 / 18 / 19 | ≥16 platform use | Double trap / software check / hardware error |
| 24-31, 48-63 | — | Designated for custom use |
Table 17: when several exceptions collide
| Exception | |
|---|---|
| 1 (highest) | Instruction address breakpoint (trigger on PC) |
| 2 | Fetch page fault or access fault during address translation (first encountered) |
| 3 | Instruction access fault (physical) |
| 4 | Illegal instruction |
| 5 | Instruction address misaligned |
| 6 | Environment call (8/9/11), then environment break (3) |
| 7 | Load/store address breakpoint (watchpoint) |
| 8 | [Optionally] load/store misaligned — OR after translation faults |
| 9 | Load/store page fault or access fault during translation |
| 10 (lowest) | Load/store access fault (physical), then misaligned if not taken earlier |
3.1.16 mtval
mtval mtval Trap value: faulting virtual address (fetch/load/store faults; portion address for misaligned/split cases) or faulting instruction bits on illegal-instruction (right-justified), or software-check code; 0 when uninformative. WARL; may be read-only zero platform-wide. defined in ch. II·3 — open in glossary carries the trap’s payload (or zero — the platform defines which exceptions must be informative):
- Faulting virtual address for breakpoint/misaligned/access/page faults on fetch, load, or store — including the portion address for a misaligned or page-straddling access (mepc still points at the instruction start).
- The faulting instruction bits (right-justified) on illegal-instruction — the emulation fast path.
- Software-check code (2 = landing pad, 3 = shadow stack).
- With paging on, even physical access faults report the virtual address — cheaper datapaths.
3.1.17–3.1.18 mconfigptr & menvcfg
mconfigptr (read-only, MXLEN-aligned) points at a platform
configuration structure (format not yet standardized; zero legal).
menvcfg (64-bit, exists iff U-mode) is where M-mode switches on
features for the modes below:
menvcfg (0x30A)
Hardware Designer Notes
The mcause/mtval writeback muxes and the Table 17 priority encoder are one RTL block — generate them from a single exception-source table in your design database so RTL, DV, and documentation can’t drift. The custom-use code ranges (24-31, 48-63) are where your accelerator’s faults belong.
Minimal Linux-boot hart MUST
- Report causes per Table 16 and resolve collisions per Table 17 — including the translate-before-misalign order if you support any misaligned accesses
- Fill mtval per the platform contract you document (address faults: yes; illegal-instruction bits: strongly recommended)
- Gate S-mode stimecmp on menvcfg.STCE and cache-block ops on CBZE/CBCFE/CBIE
MAY simplify / trap-and-emulate
- Hardwire mtval to zero platform-wide (legal, hostile to software — avoid)
- Leave every optional menvcfg field read-only zero until its extension lands
Check yourself — causes, priorities & mtval
1.How does a trap handler distinguish interrupts from exceptions in one instruction?
2.One instruction is simultaneously: at a misaligned target, an illegal encoding, and its fetch page-faults. What does mcause report?
3.On an illegal-instruction trap, what may mtval usefully contain?
4.Which menvcfg bit must be set for Linux's modern timer path (Sstc) to work in S-mode?