Tables 4–7 allocate every currently-defined CSR address. Here they are as one searchable map — filter by privilege class (URW/URO, SRW/SRO, HRW/HRO, MRW/MRO, DRW) or search by name/function. Not every register exists on every implementation: unimplemented addresses simply raise illegal-instruction.
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| CSR | Priv | Address | Group | Function |
|---|---|---|---|---|
| fflags | URW | 0x001 | FP | Accrued exception flags (NV/DZ/OF/UF/NX) |
| frm | URW | 0x002 | FP | Dynamic rounding mode |
| fcsr | URW | 0x003 | FP | frm + fflags combined |
| vstart | URW | 0x008 | Vector | Vector start position |
| vxsat | URW | 0x009 | Vector | Fixed-point saturation flag |
| vxrm | URW | 0x00A | Vector | Fixed-point rounding mode |
| vcsr | URW | 0x00F | Vector | Vector control and status |
| vl | URO | 0xC20 | Vector | Vector length |
| vtype | URO | 0xC21 | Vector | Vector data type |
| vlenb | URO | 0xC22 | Vector | Vector register length in bytes |
| ssp | URW | 0x011 | CFI | Shadow stack pointer (Zicfiss) |
| seed | URW | 0x015 | Crypto | Entropy source seed |
| jvt | URW | 0x017 | Zcmt | Table jump base vector + mode |
| cycle | URO | 0xC00 | Counters | Cycle counter (shadow of mcycle) |
| time | URO | 0xC01 | Counters | Wall-clock timer (platform mtime) |
| instret | URO | 0xC02 | Counters | Instructions retired (shadow of minstret) |
| hpmcounter3-31 | URO | 0xC03-0xC1F | Counters | Performance counters (shadows) |
| cycleh… | URO | 0xC80-0xC9F | Counters | RV32 high halves of the above |
| sstatus | SRW | 0x100 | S trap setup | Supervisor status (restricted mstatus view) |
| sie | SRW | 0x104 | S trap setup | Supervisor interrupt-enable |
| stvec | SRW | 0x105 | S trap setup | Supervisor trap vector base + mode |
| scounteren | SRW | 0x106 | S trap setup | Counter access for U-mode |
| senvcfg | SRW | 0x10A | S config | Supervisor environment configuration |
| scountinhibit | SRW | 0x120 | S counters | Supervisor counter-inhibit (Smcdeleg) |
| sscratch | SRW | 0x140 | S trap handling | Supervisor scratch |
| sepc | SRW | 0x141 | S trap handling | Supervisor exception PC |
| scause | SRW | 0x142 | S trap handling | Supervisor trap cause |
| stval | SRW | 0x143 | S trap handling | Supervisor trap value (bad addr/insn) |
| sip | SRW | 0x144 | S trap handling | Supervisor interrupt-pending |
| scountovf | SRO | 0xDA0 | S counters | Count-overflow bits (Sscofpmf) |
| siselect/sireg* | SRW | 0x150-0x157 | S indirect | Indirect CSR access window (Sscsrind) |
| satp | SRW | 0x180 | S translation | Address translation & protection: MODE/ASID/PPN |
| stimecmp | SRW | 0x14D | S timer | Supervisor timer compare (Sstc) |
| scontext | SRW | 0x5A8 | Debug | Supervisor context for triggers |
| srmcfg | SRW | 0x181 | QoS | Resource management config (Ssqosid) |
| sstateen0-3 | SRW | 0x10C-0x10F | S stateen | State-enable gates for U-mode |
| sctrctl/sctrstatus/sctrdepth | SRW | 0x14E/0x14F/0x15F | CTR | Control transfer records (Smctr) |
| hstatus | HRW | 0x600 | H trap setup | Hypervisor status |
| hedeleg/hideleg | HRW | 0x602/0x603 | H trap setup | Delegation to VS-mode |
| hie/hip/hvip | HRW | 0x604/0x644/0x645 | H interrupts | VS-level interrupt enable/pending/inject |
| hcounteren | HRW | 0x606 | H trap setup | Counter access for VS/VU |
| hgeie | HRW | 0x607 | H interrupts | Guest external interrupt enables |
| hgeip | HRO | 0xE12 | H interrupts | Guest external interrupt pending |
| henvcfg | HRW | 0x60A | H config | Hypervisor environment configuration |
| htimedelta | HRW | 0x605 | H timer | Guest time offset |
| htval/htinst | HRW | 0x643/0x64A | H trap handling | Guest trap value / transformed instruction |
| hgatp | HRW | 0x680 | H translation | Guest (G-stage) address translation |
| vsstatus/vsie/vstvec … | HRW | 0x200/0x204/0x205 … | VS twins | Virtual-supervisor copies of the S CSRs |
| vsatp | HRW | 0x280 | VS twins | VS-stage address translation |
| vstimecmp | HRW | 0x24D | VS twins | Virtual supervisor timer compare |
| mvendorid | MRO | 0xF11 | M info | Vendor ID (JEDEC) |
| marchid | MRO | 0xF12 | M info | Microarchitecture ID |
| mimpid | MRO | 0xF13 | M info | Implementation version |
| mhartid | MRO | 0xF14 | M info | Hart ID (one hart must be 0) |
| mconfigptr | MRO | 0xF15 | M info | Pointer to config structure |
| mstatus | MRW | 0x300 | M trap setup | Machine status: privilege stack, interrupt enables, FS/XS, endianness… |
| misa | MRW | 0x301 | M trap setup | ISA width + extension letters (WARL) |
| medeleg/mideleg | MRW | 0x302/0x303 | M trap setup | Exception/interrupt delegation to S-mode |
| mie | MRW | 0x304 | M interrupts | Machine interrupt-enable |
| mtvec | MRW | 0x305 | M trap setup | Machine trap vector base + mode (direct/vectored) |
| mcounteren | MRW | 0x306 | M trap setup | Counter access for S-mode |
| mstatush | MRW | 0x310 | M trap setup | RV32: upper mstatus bits |
| mscratch | MRW | 0x340 | M trap handling | Machine scratch (trap-handler stack anchor) |
| mepc | MRW | 0x341 | M trap handling | Machine exception PC (WARL, IALIGN-masked) |
| mcause | MRW | 0x342 | M trap handling | Trap cause: interrupt bit + code |
| mtval | MRW | 0x343 | M trap handling | Faulting address / instruction bits |
| mip | MRW | 0x344 | M interrupts | Machine interrupt-pending |
| mtinst/mtval2 | MRW | 0x34A/0x34B | M trap handling | H-extension guest-trap details |
| menvcfg | MRW | 0x30A | M config | Environment config (FIOM, CBIE, PBMTE, STCE…) |
| mseccfg | MRW | 0x747 | M config | Security config (PMP enhancements, Zkr) |
| pmpcfg0-15 | MRW | 0x3A0-0x3AF | PMP | PMP configuration bytes (RV64: even only) |
| pmpaddr0-63 | MRW | 0x3B0-0x3EF | PMP | PMP address registers (WARL grain) |
| mstateen0-3 | MRW | 0x30C-0x30F | M stateen | State-enable gates for S/U |
| mnscratch/mnepc/mncause/mnstatus | MRW | 0x740-0x744 | RNMI | Resumable NMI state (Smrnmi) |
| mcycle | MRW | 0xB00 | M counters | Cycle counter (writable master) |
| minstret | MRW | 0xB02 | M counters | Instret counter (writable master) |
| mhpmcounter3-31 | MRW | 0xB03-0xB1F | M counters | HPM counter masters |
| mcountinhibit | MRW | 0x320 | M counters | Stop counters (power/measurement) |
| mhpmevent3-31 | MRW | 0x323-0x33F | M counters | Event selectors |
| mcyclecfg/minstretcfg | MRW | 0x321/0x322 | M counters | Privilege-mode filtering (Smcntrpmf) |
| tselect/tdata1-3 | MRW | 0x7A0-0x7A3 | Debug | Trigger module (M-visible) |
| dcsr/dpc/dscratch… | DRW | 0x7B0-0x7BF | Debug | Debug-mode-only — M access traps |
Hardware Designer Notes
This table is the register-file floorplan for Part II: each following chapter specifies the fields behind one group. Budget note — the genuinely stateful CSRs for a minimal Linux hart number only about thirty; the rest of the 4096-entry space is decode-and-trap.
Minimal Linux-boot hart MUST
- Implement the Linux-boot set: M info (mhartid may hardwire per-hart), M trap setup/handling, mcounteren, the S twins + satp + stimecmp, menvcfg, and the counter file
- Trap accesses to everything you leave out — unimplemented CSRs are not read-as-zero
- Alias sstatus/sie/sip as masked views of mstatus/mie/mip, not separate flops
MAY simplify / trap-and-emulate
- Skip whole optional blocks (H, vector, indirect-access, CTR, RNMI, stateen) on a first Linux core
- Hardwire the info registers (mvendorid=0 is legal for non-commercial)
Check yourself — the CSR map
1.Which four CSRs form the minimal machine trap-handling set every trap handler touches?
2.Why does sstatus (0x100) exist when S-mode state already lives in mstatus (0x300)?
3.For a minimal Linux-boot RV64 hart (no H, no vector, no debug), roughly which CSR groups from the listing are mandatory?
3 questions