RV32I reserves a large slab of encoding space for HINT instructions hint instruction An encoding (mostly integer ops with rd=x0, or null-effect FENCEs) that changes no architectural state except pc/counters; implementations may ignore it or execute it as a dead operation. Never traps. defined in ch. I·2 — open in glossary — encodings that communicate performance information to the microarchitecture while changing no architectural state except pc and performance counters. The design trick: nearly all HINTs are ordinary computational instructions with rd = x0, plus FENCE encodings whose predecessor or successor set is null. A core that knows nothing about hints executes them as dead operations at zero hardware cost; a core that recognizes them may do something smart; both are conforming, because implementations are always allowed to ignore hints.
The HINT map
91% of the space is reserved for future standard hints; the rest is permanently custom. Standard code points already burned in (Table 5):
| Constraints | Code points | Purpose | |
|---|---|---|---|
| LUI / AUIPC / ANDI / ORI / XORI | rd=x0 | 2^20 / 2^20 / 2^17 ×3 | Future standard use |
| ADDI | rd=x0, and rs1≠x0 or imm≠0 | 2^17−1 | Future standard use |
| ADD | rd=x0, rs1=x0, rs2=x2–x5 | 4 | NTL.P1 / NTL.PALL / NTL.S1 / NTL.ALL |
| ADD (rest) | rd=x0, other rs1/rs2 | 2^10−32 + 2^8 | Future standard use |
| SLLI / SRAI | rd=x0, rs1=x0, shamt=31 / 7 | 1 + 1 | Semihosting entry/exit markers |
| SUB/AND/OR/XOR/SLL/SRL/SRA | rd=x0 | 2^10 each | Future standard use |
| FENCE | fm=0, pred=0 or succ=0 (rs1/rd variants) | ~2×(2^10−63)+30 | Future standard use |
| FENCE | rd=rs1=x0, fm=0, pred=W, succ=0 | 1 | PAUSE |
| SLTI / SLTIU | rd=x0 | 2^17 each | CUSTOM |
| SLLI / SRLI / SRAI (non-marker) | rd=x0, excl. semihosting points | ~2^10 each | CUSTOM |
| SLT / SLTU | rd=x0 | 2^10 each | CUSTOM |
Hardware Designer Notes
The decode cost of HINT compliance is zero by construction — that’s the whole design. If you do act on a hint (say, PAUSE throttling the fetch unit in a spin loop), keep the action microarchitectural only: no architectural state may change, and unrecognized-hint behavior must be indistinguishable from a plain dead instruction. When allocating your own hints, stay inside the CUSTOM rows — the standard rows are a compatibility time bomb (the semihosting markers show standard hints do get minted).
Minimal Linux-boot hart MUST
- Execute every HINT encoding as its underlying instruction (dead write to x0 / null fence) — advancing pc and counters, never trapping
MAY simplify / trap-and-emulate
- Recognize specific hints (PAUSE, NTL.*) and act on them — or ignore all of them
- Use the CUSTOM-designated rows for product-specific hints without breaking conformance
Check yourself — HINTs
1.Your minimal core meets ADD x0, x5, x7 (a HINT encoding it doesn't recognize). What's the cheapest correct behavior?
2.Which encodings carry the standard PAUSE hint and the NTL.* hints?
3.Can you use SLTI rd=x0 encodings for your own accelerator's hints in a conforming design?