Every region of the physical address space has fixed properties — what widths it supports, whether atomics work, how it orders, whether reads have side effects. RISC-V names these Physical Memory Attributes pma Physical Memory Attributes: per-region fixed hardware properties (main-memory vs I/O, access widths, atomicity levels AMONone..AMOArithmetic, reservability RsrvNone/NonEventual/Eventual, misaligned granule, ordering channels, coherence/cacheability, idempotency) checked by a dedicated PMA checker; violations = precise access faults where possible. defined in ch. II·3 — open in glossary and checks them in a dedicated PMA checker on the physical address — deliberately not in page tables, keeping platform physics out of the virtualized layer. Violations should trap as precise access-faults (imprecise bus-error interrupts only where legacy buses force it).
The attribute catalog
| Values | Linux-hart baseline | |
|---|---|---|
| Region class | Main memory vs I/O | DDR = main memory; devices, and anything odd, = I/O |
| Access types | Supported widths, misaligned support, burst (for DMA programming); PT-walk read/write support per region | All widths on DDR; cacheable main memory must support page-table walks |
| AMO support | AMONone < AMOSwap < AMOLogical < AMOArithmetic (+ Zacas: AMOCASW/D/Q) | AMOArithmetic on all of DDR |
| Reservability | RsrvNone / RsrvNonEventual / RsrvEventual | RsrvEventual on DDR — the constrained-loop guarantee of ch. I·13 lives or dies here |
| Misaligned atomicity granule | MAGnn (power-of-two bytes) | Optional; see ch. I·13/I·18 semantics |
| Ordering | Main: RVWMO/RVTSO (coherent). I/O: relaxed, or strongly ordered with channels 0 (point-to-point) / 1 (global = fence io,io around every access) / N (same-channel) | DDR RVWMO; device MMIO usually strongly ordered ch. 0 |
| Coherence & cacheability | Per-region; M-mode-managed platform settings | DDR coherent+cacheable; MMIO non-cacheable |
| Idempotency | Main memory: idempotent. I/O: reads/writes separately declarable non-idempotent → no speculative or redundant accesses (bounded NAPOT read-around allowed, ≤ min page size) | Device FIFOs/doorbells non-idempotent; misaligned access to them should ACCESS-fault (don’t emulate!) |
Hardware Designer Notes
For your SoC this section is a memory-map spreadsheet: one row per region, one column per attribute — and that spreadsheet IS the PMA checker ROM, the DMA-engine programming guide, and the device-tree content. The Linux-boot must-have row: all of DDR as coherent, cacheable, RVWMO main memory with AMOArithmetic + RsrvEventual and page-table-walk support.
Minimal Linux-boot hart MUST
- Check PMAs on the PHYSICAL address of every access — after translation, in parallel with PMP
- Trap violations precisely as access-faults wherever the bus allows
- Bypass caches entirely for non-cacheable regions, even on hits
- Suppress speculative/redundant implicit accesses to non-idempotent regions (fetch read-around only within the bounded NAPOT window)
MAY simplify / trap-and-emulate
- Hardwire the whole PMA map for a fixed SoC — a ROM table keyed by address range
- Report device bus errors as imprecise interrupts where precision is impossible
Check yourself — PMAs
1.Why does RISC-V check PMAs in a dedicated checker instead of encoding them in page-table entries like many ISAs?
2.Your DDR region should support Linux. Which atomicity/reservability PMAs does it need?
3.A strongly ordered I/O region is assigned channel 1. What ordering does an access to it get?
4.A misaligned store targets a non-idempotent I/O region your core won't handle natively. Which exception, and why does it matter?