3.1.19-5mseccfg, the Platform Timer, Privileged Instructions, Reset & NMI

The rest of the machine-level core: the security-configuration CSR, the timer that drives every OS tick, the four privileged instructions, and what reset actually guarantees.

3.1.19 mseccfg

Exists when any contributing extension does (else reserved). Per Figure 2 (one of the few priv figures that survived — transcribed from the text layout):

3.2 mtime & mtimecmp: the heartbeat

Both are memory-mapped, both 64-bit on RV32 and RV64. mtime mtime/mtimecmp Memory-mapped 64-bit platform timer: mtime = constant-frequency wall clock (shared, own clock domain); MTIP pending iff mtime >= mtimecmp (unsigned), cleared by writing mtimecmp. time CSR is a read-only shadow. RV32 write order: low=-1, high, low. defined in ch. II·3 — open in glossary counts wall-clock ticks at a constant, platform-published frequency; MTIP is pending iff mtime ≥ mtimecmp (unsigned), cleared by writing mtimecmp. The time CSR is a read-only shadow. Two software contracts worth memorizing:

# RV32: glitch-free 64-bit comparand update (a1:a0 = new value)
li   t0, -1
sw   t0, 0(t1)     # low ← -1: comparand can't shrink transiently
sw   a1, 4(t1)     # high ← new
sw   a0, 0(t1)     # low ← new

and: MTIP reflection is eventual — a handler that bumps mtimecmp and returns immediately may take one spurious timer interrupt. Tolerate it.

3.3 The privileged instructions

3.4–3.5 Reset and NMI

Reset guarantees little — deliberately: reset state Mode=M, MIE=MPRV=0, MBE=0, misa maximal, no reservation, pc=reset vector, mcause=reset cause, PMP A/L=0, mnstatus.NMIE=0, mseccfg MML/MMWP/RLB/MLPE=0; no WARL field illegal; everything else UNSPECIFIED. defined in ch. II·3 — open in glossary mode = M; MIE = MPRV = 0; MBE = 0 (if LE supported); misa maximal; no LR reservation; pc = implementation-defined reset vector; mcause = reset cause (0 = most complete reset); PMP entries’ A/L = 0; mnstatus.NMIE = 0; mseccfg’s MML/MMWP/RLB/MLPE = 0; SEED fields defined; no WARL field illegal — and everything else UNSPECIFIED.

NMIs (hardware-error only) jump to their own implementation-defined M-mode vector regardless of every enable bit; mepc/mcause are written (Interrupt=1, code 0 = unknown source), state is not reset — an NMI can land mid-handler and overwrite mepc/mcause, which is exactly the hole the Smrnmi resumable-NMI extension (ch. II·8) plugs.