The Road to Linux Boot

Building a Linux-bootable RISC-V hart, stage by stage

The RISC-V spec is a menu, not a recipe. This is the recipe: the order in which a hardware team implements the architecture to reach a hart that boots Linux, then a hart that is RVA23-conformant. Each page in the book carries a Linux boot tag — required, recommended, or optional — and this roadmap threads them into a build order.

  1. 1

    Fetch, decode, execute: the base integer core

    RV64I plus the M (multiply/divide), A (atomics), and C (compressed) extensions, CSR access (Zicsr), and FENCE.I (Zifencei). This is a hart that runs bare-metal RV64GC code.

    I·2 RV32I Base Integer Instruction Set, Version 2.1 I·4 RV64I Base Integer Instruction Set, Version 2.1 I·5 "Zifencei" Extension for Instruction-Fetch Fence, Version 2.0 I·6 "Zicsr" Extension for Control and Status Register (CSR) Instructions, Version 2.0 I·7 "Zicntr" and "Zihpm" Extensions for Counters, Version 2.0
  2. 2

    Floating point & counters

    F and D single/double-precision floating point (the ABI assumes them), the Zicntr time/cycle/instret counters, and Zihpm performance monitors.

    I·21 "F" Extension for Single-Precision Floating-Point, Version 2.2 I·22 "D" Extension for Double-Precision Floating-Point, Version 2.2 I·13 "A" Extension for Atomic Instructions, Version 2.1
  3. 3

    The memory model

    RVWMO — the rules every load, store, fence, and atomic obeys. Get the ordering right before multicore, or debugging is impossible.

    I·18 RVWMO Memory Consistency Model, Version 2.0
  4. 4

    Machine mode: traps, CSRs, the boot mode

    M-mode is where the hart resets. mstatus/mtvec/mepc/mcause, delegation (medeleg/mideleg), the interrupt architecture, and PMP for isolating firmware from the OS.

    II·3 Machine-Level ISA, Version 1.13 II·7 "Smcntrpmf" Cycle and Instret Privilege Mode Filtering, Version 1.0
  5. 5

    Supervisor mode & virtual memory

    The register file Linux lives in: the supervisor CSRs, SFENCE.VMA, and the Sv39/48/57 page-table walker. This is the single biggest hardware block — the MMU.

    II·12 Supervisor-Level ISA, Version 1.13
  6. 6

    The timer & the SBI contract

    Sstc (stimecmp) gives S-mode its own timer without an SBI round trip on every scheduler tick; the counter-overflow interrupt (Sscofpmf) makes perf work.

    II·13 "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0 II·14 "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0
  7. 7

    Profile-complete: the RVA23 application core

    The bit-manipulation B extension, vectors (V), and the CFI/pointer-masking security features that a modern distro binary now assumes. Optional to boot, mandatory to be conformant.

    I·30 Bit Manipulation Extensions I·31 "V" Standard Extension for Vector Operations, Version 1.0 I·34 Control-flow Integrity (CFI)

Every required page, in order

The 36 pages tagged required to boot Linux — the irreducible core.

Then the recommended pages

37 pages that a practical Linux system wants — Sstc, Sscofpmf, the B extension, CMOs, PAUSE — but that a minimal boot can defer.

Everything else — the whole of Part III (vectors, crypto, Zfa/Zfh, Zicond, and the rest) — is the optional side-shelf: full-depth, RVA23-relevant, but not on the critical path to a booting kernel. Build the core first; reach for these when the workload demands them.