Sv57
The fifth level: VPN[4] at bits 56:48, canonicality above bit 56, petapages (256 TiB) atop Sv48’s sizes. The PTE collapses the distinction anyway — same bits 63:54 and 9:0 as Sv39/48, LEVELS=5, PTESIZE=8. Sv57 support mandates Sv48 support, which mandates Sv39.
Svnapot — TLB reach without new page sizes
A leaf PTE with N=1 declares itself part of a NAPOT (naturally
aligned power-of-two) range whose translations differ only in the low
PPN bits. One encoding is standardized: level 0, ppn[3:0] = 1000 →
64 KiB (napot_bits = 4); every other N=1 pattern page-faults.
Implicit reads behave as if ppn[0][3:0] were replaced by
vpn[0][3:0] — so the TLB may hold the whole region as one entry, or
16 synthesized 4 KiB entries, at its whim.
The OS contract is strict: all 16 PTEs of a region must agree (update = invalidate-all → fence → rewrite), and because hardware may never consult the specific PTE the algorithm names, A/D bits must be queried across every alias. With H, NAPOT works in G-stage too.
Svpbmt — per-page memory types
| Requested attributes | Ordering when it overrides the PMA | |
|---|---|---|
| 0 — PMA | None: the physical region’s own attributes stand. | Whatever the PMA says. |
| 1 — NC | Non-cacheable, idempotent, weakly-ordered, main memory. | On I/O-backed pages: RVWMO, but accesses count as BOTH I/O and memory for FENCE/.aq/.rl. |
| 2 — IO | Non-cacheable, non-idempotent, strongly-ordered (channel 0). | On RAM-backed pages: strong I/O ordering, dual I/O+memory fence membership. |
Aliases with different attributes are software’s problem: two
non-cacheable flavors need fence iorw, iorw between them; differing
cacheability needs fence iorw, iorw; cbo.flush; fence iorw, iorw
or coherence is genuinely lost. Under the H extension the override
stacks twice: G-stage PBMT refines the PMA into intermediate
attributes, VS-stage PBMT refines those into final ones (VS page-table
walks themselves use the intermediate set).
Svinval — pipelined invalidation
| Semantics | |
|---|---|
| SINVAL.VMA (funct7 0001011) | Invalidates exactly what SFENCE.VMA(rs1, rs2) would — but is ordered ONLY against the two bracket fences below. |
| SFENCE.W.INVAL (0001100, rs2=x0) | Prior visible stores ordered before subsequent SINVAL.VMAs. |
| SFENCE.INVAL.IR (0001100, rs2=x1) | Prior SINVAL.VMAs ordered before subsequent implicit page-table references. |
| HINVAL.VVMA / HINVAL.GVMA (0010011 / 0110011) | H-extension analogues replacing HFENCE.VVMA/GVMA; HINVAL.GVMA filters by VMID instead of ASID. |
W.INVAL → SINVAL×N → INVAL.IR, executed in order (not necessarily
consecutively), equals one SFENCE.VMA per SINVAL — but the pipeline
drain happens twice total instead of N times. Permissions mirror the
fences they replace (U-mode illegal, TVM traps
SINVAL.VMA; the two bracket fences are never TVM-trapped — they only
order). Simple implementations: SINVAL.VMA = SFENCE.VMA, brackets =
no-ops.
Svadu, Svvptc, Svrsw60t59b
- Svadu: makes
menvcfg.ADUE(andhenvcfg.ADUE) writable, enabling the hardware A/D-update scheme from the previous page; disabled → Svade faulting applies. - Svvptc: stores flipping a PTE’s V bit 0→1 become visible to the walker in bounded time without any fence — deleting the map-in SFENCE.VMA from every demand-paging fault, at the cost of an occasional gratuitous (retried) page fault. Implementation routes: don’t cache V=0 entries, bounded-timer eviction, or walker-coherent TLBs.
- Svrsw60t59b: PTE bits 60:59 join RSW — ignored by hardware, free for OS metadata (also in G-stage PTEs with H). Depends on Sv39.
Hardware Designer Notes
Cost ranking for a small core: Svrsw60t59b (mask two bits from the reserved-check) < Svvptc (a fill-policy rule) < Svinval (decode aliases) < Svnapot (TLB entry format or fill logic) < Svadu (walker store path + CAS) < Svpbmt (attribute plumbing through the whole memory hierarchy).
Minimal Linux-boot hart MUST
- Fault on reserved N/PBMT patterns exactly (N=1 with ppn[3:0]≠1000; PBMT=3; nonzero PBMT/N on non-leaf) — reserved-encoding leniency here breaks forward compatibility
- If Svpbmt: plumb the 2-bit type into the memory system so NC/IO pages bypass the caches and hit the right ordering channel
- If Svvptc: guarantee the bounded-visibility property structurally (e.g. never fill V=0 entries into the TLB)
MAY simplify / trap-and-emulate
- Skip all of these for a first Linux boot — none are required, though RVA23 mandates Svnapot + Svpbmt (Svadu/Svvptc are the profile-optional ones)
- Implement Svinval as pure decode aliases (SINVAL=SFENCE.VMA, brackets=no-op) and upgrade to real pipelining when TLB-shootdown latency matters
- Treat a NAPOT PTE as 16 ordinary TLB fills — correctness needs no special entry format
Check yourself — Sv57 & the Sv* extensions
1.What does a Svnapot 64 KiB NAPOT PTE (N=1, ppn[3:0]=1000) change in the walk?
2.A main-memory page is mapped with PBMT=IO. What ordering do accesses to it obey?
3.Why does Svinval split SFENCE.VMA into three instructions?
4.What does Svvptc let an OS skip, and at what price?