Perf profiling writes counters constantly — clearing overflow state on every sample, reloading counters on every context switch. Without help, each write is an SBI trap to M-mode. Smcdeleg/Ssccfg counter delegation Smcdeleg/Ssccfg: with menvcfg.CDE=1, counters whose mcounteren bit is set become S-mode WRITABLE via siselect 0x40+i / sireg* (Table 25 map; 0x41 = hole, mtime is not supervisor-managed; MINH masked to 0). Adds scountinhibit as a masked mcountinhibit alias. Cuts M-mode trap latency out of perf sampling and context switches. defined in ch. II·9 — open in glossary (always implemented together) let M-mode hand chosen counters to S/HS for direct writes, through the indirect-CSR window.
The delegation map
Counter i is delegated iff menvcfg.CDE = 1 ∧ mcounteren[i] = 1.
Then siselect = 0x40 + i exposes its state:
| sireg (low) | sireg4 (high, RV32) | sireg2 (config) | sireg5 (cfg-high, RV32) | |
|---|---|---|---|---|
| 0x40 | cycle (Zicntr) | cycleh | cyclecfg (Smcntrpmf) | cyclecfgh |
| 0x41 | — hole: always illegal — | — | — | — |
| 0x42 | instret | instreth | instretcfg | instretcfgh |
| 0x43…0x5F | hpmcounter3…31 (Zihpm) | …h twins | hpmevent3…31 (MINH masked; Sscofpmf for OF semantics) | …h twins (Sscofpmf) |
Illegal-instruction for: any access with CDE=0; sireg3/sireg6 (unused); sireg4/sireg5 when XLEN=64; the 0x41 hole; a non-delegated counter; or missing underlying extensions. Under H: VS-mode access to this range raises virtual-instruction when CDE=1 (the hypervisor emulates a vPMU — guest counters aren’t hardware-delegated), and vsireg* in this range is illegal even from M/S.
scountinhibit and virtualized overflow
scountinhibit (0x120) is a masked alias of mcountinhibit:
delegated counters’ bits are read-write, the rest read-only zero
(CDE=0 → illegal; VS/VU → virtual-instruction). For overflow
interrupts: with H + Sscofpmf + CDE=1, VS/VU reads of scountovf raise
virtual-instruction; and with AIA present, the LCOFI bits of
mvip/mvien (and hvip/hvien under H) must be writable so virtual
counter-overflow interrupts can be injected into S and VS guests.
Hardware Designer Notes
Hardware cost is a routing table and write masks; the value is measurable perf-overhead reduction in any OS that samples. If you built p05’s router, this extension is one weekend: 32 select entries pointing at registers you already have.
Minimal Linux-boot hart MUST
- Route 0x40+i selects onto the existing machine counter/event registers with delegation write-masks
- Mask MINH (bit 62) to zero in every sireg* view
- Implement the exception matrix exactly — especially the 0x41 hole and the CDE=1 virtual-instruction cases under H
MAY simplify / trap-and-emulate
- Skip the extension until Zihpm + perf matter — Linux falls back to SBI PMU calls
- Implement scountinhibit as a masked read/write port on mcountinhibit (no new flops)
Check yourself — counter delegation
1.What makes counter i writable from S-mode under Smcdeleg?
2.Why is siselect=0x41 a hole that always raises illegal-instruction?
3.S-mode reads a delegated hpmevent through sireg2. What does bit 62 (MINH) show?