§31.20 closes the chapter with the full funct6 × funct3 encoding tables. Rather than transcribe six pages of grid, here is the map by which to read them — which categories live where, keyed to the pages that defined them:
| Instruction families (defining page) | |
|---|---|
| OPIVV / OPIVX / OPIVI (000/100/011) | add/sub/rsub, logicals, shifts, compares, min/max, saturating & averaging fixed-point, narrowing shifts & clips, merges/moves, slides, gathers — the “I” integer side. (Pages VIII, IX, XIV.) |
| OPMVV / OPMVX (010/110) | Widening adds/subs, multiplies, divides, MACs, extensions, reductions, mask logicals & scans (vcpop/vfirst/vmsbf/viota/vid), scalar taps vmv.x.s/s.x, vcompress, whole-register moves. (Pages VIII, IX, XII, XIII, XIV.) |
| OPFVV / OPFVF (001/101) | The FP world: arithmetic, FMAs, sqrt & estimates, min/max, sign-injection, compares, classify, merges, converts, FP reductions, FP scalar taps & slides. (Pages X, XI, XII.) |
| OPCFG (111) | vsetvli / vsetivli / vsetvl. (Page V.) |
| LOAD-FP / STORE-FP overlays | All memory ops — unit-stride, strided, indexed, FOF, segments, whole-register. (Pages V, VI, VII.) |
Two run-time discovery rules make the listing usable portably:
every configuration probe is vsetvli + branch-on-vill (no traps),
and every unsupported encoding (reserved LMUL misalignments,
overlap violations, unsupported EEWs) raises illegal-instruction —
detectable, never silently wrong.
Hardware Designer Notes
That completes the V extension: 16 pages covering 103 spec pages. For the site’s hardware lens, the build-out order that works: unit-stride memory + integer lanes first (strip-mined memcpy), then FP FMA lanes, then masks/reductions, then permutation, with precise traps designed in from the LSU up. The RVA23 mandate makes all of it table stakes for application cores.
Minimal Linux-boot hart MUST
- Decode the complete funct6 map — unimplemented entries must trap as illegal, and reserved corners (vm=0 on always-unmasked ops, misaligned groups) likewise
- Cross-check your decoder against the §31.20 tables mechanically; hand-transcription of ~300 encodings WILL slip
MAY simplify / trap-and-emulate
- Generate the decoder from the riscv-opcodes machine-readable files rather than the PDF tables
Check yourself — the V listing
1.An OP-V instruction has funct3=010 (OPMVV). Which instruction families could it be?
2.How can software discover, at run time, whether the hardware supports SEW=64 at LMUL=1/2?