35.1-5"Zilsd" & "Zclsd": RV32 Load/Store Pair

Part III Linux boot: optional Vol. I (Unprivileged) pp. 576–583 · ~2 min read

RV32 lacks a native 64-bit memory move — so 64-bit values (ABI doublewords, Zdinx pairs, atomic setups) cost two word accesses. Zilsd/Zclsd recover the single instruction by reusing the RV64 LD/SD encodings, which sit unused on RV32.

The instructions (src/dest in EVEN-aligned x-register pairs; low register = low bits, endianness-independent)
InstructionsIn
ld rd, off(rs1) / sd rs2, off(rs1)32-bit encodings moving a doubleword to/from the register pair — odd first registers reserved.Zilsd
c.ldsp / c.sdspSP-relative compressed doubleword load/store.Zclsd (needs Zca)
c.ld / c.sdCompressed doubleword load/store (rs1′ form).Zclsd
Dotted-underlined cells have explanations — click one.

Two constraints matter:

  • Atomicity: a naturally-aligned (8-byte) access won’t raise an address-misaligned trap, but is not guaranteed atomic — an implementation may perform two word accesses. Atomicity holds only if the memory access is atomic and the register file supports even/odd pair write-back.
  • Resumable traps: on a load trap, the base register must retain its original value (the other pair register may already be updated), so the handler can restart. For the SP-relative compressed forms, this pins x2.

Hardware Designer Notes

A small win for RV32-heavy embedded targets: doubleword moves in one instruction (density) and, with pair write-back, atomic 64-bit loads that Zdinx and 64-bit-value ABIs appreciate. Not relevant to RV64 Linux, where LD/SD are already native.

Minimal Linux-boot hart MUST

  • Decode the RV64 LD/SD (and compressed) encodings on RV32 as pair operations; reserve odd first registers
  • Preserve the base register on load traps for resumability; the other pair register may update
  • Choose Zclsd XOR Zcf — their compressed encodings collide

MAY simplify / trap-and-emulate

  • Provide even/odd pair write-back for atomic doubleword loads; otherwise sequence two word writes (non-atomic, still correct)
  • Skip both for a minimal core — two word accesses always work, just larger and slower

Check yourself — RV32 load/store pair

1.How do Zilsd's ld/sd instructions exist on RV32 when ld/sd are 64-bit RV64 instructions?

2.Are Zilsd doubleword accesses atomic, and what must hold for resumable traps?

2 questions