2.5-8Control Transfer, Loads & Stores, FENCE, and Environment Calls

RV32I’s remaining instructions are where the ISA meets the memory system and the outside world: two jumps, six branches, eight loads/stores, one fence, and two trap generators. No delay slots anywhere — and a subtle rule worth pinning immediately: an access-fault or page-fault on the target of a jump/taken branch is reported on the target instruction, while a misaligned target is reported on the jump/branch itself.

2.5 Unconditional jumps

JAL uses the J-format: a ±1 MiB signed offset in multiples of 2, added to the JAL’s own address; pc+4 is written to rd (the link value). J offset is just JAL with rd=x0.

JALR uses the I-format: target = (rs1 + sext(imm12)) & ~1 — the least-significant bit is cleared, which slightly simplifies hardware and lets software stash a tag bit in function pointers. pc+4 goes to rd. RET = JALR x0, x1, 0.

Both raise instruction-address-misaligned if the target isn’t 4-byte aligned (impossible once C gives you IALIGN=16).

Return-address prediction is encoded implicitly. There are no hint bits; the register numbers are the hint. x1 and x5 are the two link registers, and Table 3 is the contract your RAS must implement:

JAL pushes only when rd is x1/x5.

2.5.2 Conditional branches

B-format, ±4 KiB in multiples of 2. All six compare two registers: BEQ/BNE, BLT/BLTU, BGE/BGEU — the missing four (BGT/BGTU/ BLE/BLEU) are operand swaps. A neat idiom: one BLTU index, bound checks a signed array index against a bound, because negative indices compare huge unsigned.

The misaligned-target exception fires only if the branch is taken. Software guidance baked into the ISA: lay out code so fall-through is the common path; static predictors should assume backward-taken, forward-not-taken. Use JAL (rd=x0), never an always-true branch, for unconditional jumps — wider range and no pollution of conditional predictors.

2.6 Loads and stores

RV32I is a load-store architecture load-store architecture Only loads and stores access memory; arithmetic operates solely on registers. defined in ch. I·2 — open in glossary . Effective address = rs1 + sext(imm12); loads are I-type (LW, LH/LHU, LB/LBU — sign- vs zero-extending), stores are S-type (SW, SH, SB, storing the low bits of rs2). Loads with rd=x0 still raise exceptions and side effects — the value is discarded, the access is not.

Endianness is EEI-defined, and always byte-address invariant byte-address invariance Endianness property RISC-V mandates: a byte stored at an address is returned by a byte load from that address in ANY endianness. defined in ch. I·2 — open in glossary : a byte stored at an address reads back identically in any endianness — only multi-byte ordering differs.

Alignment is a two-level contract. Accesses with natural alignment natural alignment An access is naturally aligned when its effective address is divisible by the access size in bytes. Naturally aligned loads/stores never raise address-misaligned exceptions and are atomic; misaligned behavior is EEI-defined. defined in ch. I·2 — open in glossary never misalign-trap, and are guaranteed atomic. Misaligned accesses are the EEI’s choice:

• EEI guarantees full support → delivered by hardware, by an invisible trap into the environment (M-mode emulation), or a mix by address range. Software never sees a misalignment trap — but the access may be very slow, and is not guaranteed atomic.
• EEI doesn’t guarantee it → the access may succeed or raise address-misaligned or access-fault (the latter when emulation would be wrong, e.g. a side-effecting I/O region); the EEI defines whether the trap is contained or fatal.

2.7 FENCE

FENCE pred, succ orders the predecessor set fence predecessor/successor sets FENCE names two subsets of {device Input, device Output, memory Reads, memory Writes}: no other hart/device may observe any successor-set operation before any predecessor-set operation. defined in ch. I·2 — open in glossary before the successor set, each any combination of Input, Output, Read, Write — as observed by other harts, devices, and coprocessors. Memory-mapped I/O is ordered via I/O bits (device input/ output), ordinary cacheable memory via R/W. One explicit hole: a device observing a write through a non-memory channel (say, an interrupt wire) is outside FENCE’s jurisdiction entirely.

FENCE.TSO (fm=1000, RW,RW) orders predecessor loads before all successors and predecessor stores before successor stores — everything except store-to-load. Implementing it as a plain full FENCE is explicitly correct, since full ordering is a superset. The forward-compatibility rule generalizes: all reserved fm/pred/succ configurations execute as normal fences, and a simple core may execute every FENCE as a full conservative fence.

2.8 ECALL and EBREAK

The SYSTEM major opcode splits into CSR read-modify-writes (ch. I·6) and the rest. RV32I’s two are precise requested traps: ECALL ecall SYSTEM instruction raising a precise requested trap to the execution environment — the service-call mechanism (parameters per EEI, usually in registers). defined in ch. I·2 — open in glossary requests a service from the execution environment (arguments per the EEI’s ABI, usually in registers); EBREAK ebreak SYSTEM instruction returning control to a debugging environment; also used for semihosting via the fixed sequence slli x0,x0,0x1f; ebreak; srai x0,x0,7 (all 32-bit forms). defined in ch. I·2 — open in glossary hands control to a debugger. Simple cores may funnel all SYSTEM instructions to one trap handler.

Semihosting reuses EBREAK inside a fixed, uncompressed 32-bit sequence — slli x0,x0,0x1f; ebreak; srai x0,x0,7 — so a debugger can distinguish a semihosting call from an ordinary breakpoint (the shift-NOPs are themselves HINT encodings).