This is the register file Linux actually lives in. The design rule that
shapes everything: S-mode sees no evidence that M-mode exists — no
M CSRs, no M interrupt bits, timer and IPI services arriving through an
SBI sbi/see Supervisor Binary Interface / Supervisor Execution Environment: the OS-to-firmware contract (user+supervisor ISA plus SBI calls). One SBI lets one OS binary run on a bootloader SEE, a hypervisor VM, or a simulator. Linux's SEE is typically OpenSBI in M-mode.
defined in ch. II·1 — open in glossary
or, with Sstc, directly. And almost every
register here is a subset view of its machine-mode twin: reading or
writing a field of sstatus/sip/sie reads or writes the
homonymous field of mstatus/mip/mie —
same flops, different window.
sstatus — the operating state
sstatus (0x100), SXLEN=64 — Figure 18
stvec, sip and sie
stvec mirrors mtvec: BASE[SXLEN-1:2] (4-byte aligned, WARL) plus
MODE[1:0] — 0 = Direct (everything to BASE), 1 = Vectored
(interrupts to BASE + 4×cause, so the S-timer lands at BASE + 0x14;
exceptions still go to BASE), ≥2 reserved.
Interrupt i traps to S-mode iff sip[i] ∧ sie[i], and either the
hart is in S with sstatus.SIE set or it’s running less privileged
than S. The check must resolve in bounded time after sip changes, and
immediately after SRET or any write to sip/sie/sstatus.
| Bit | sip behavior | Source & handling | |
|---|---|---|---|
| SEIP/SEIE — external | 9 | read-only | Set/cleared by the platform interrupt controller (PLIC/APLIC). Highest priority. |
| STIP/STIE — timer | 5 | read-only | Without Sstc: set/cleared by the SEE (SBI call). With Sstc: reflects time ≥ stimecmp directly. |
| SSIP/SSIE — software | 1 | read/write | The IPI bit: remote harts (via implementation means) or the local hart set it; handler clears it by writing 0. |
| LCOFIP/LCOFIE — counter overflow | 13 | read/write | Sscofpmf: any mhpmevent.OF becoming set. Read-only 0 without it. |
Simultaneous supervisor interrupts resolve in decreasing priority
SEI, SSI, STI, LCOFI. Discovery is write-ones-readback on sie: a
bit must be writable iff its interrupt can ever pend; unimplemented
sources read zero.
Counters, sscratch, sepc
scounteren (32-bit, must exist, every bit may be RO-0) gates U-mode
access to cycle/time/instret/hpmcounterN — an access succeeds
only when the bit is set in both mcounteren and
scounteren; otherwise illegal-instruction. sscratch is the classic
trap-entry pivot: csrrw sp, sscratch, sp swaps in the kernel stack
pointer with zero temporaries. sepc (WARL, must hold all valid
virtual addresses; bit 0 always zero, bit 1 read-masked while
IALIGN=32) captures the interrupted PC.
scause
One Interrupt bit atop a WLRL exception code (values 0–31 must be representable). Interrupts: 1 SSI, 5 STI, 9 SEI, 13 LCOFI, ≥16 platform. Exceptions use the mcause table verbatim — misaligned/access/illegal/breakpoint/ecall (8 from U, 9 from S)/page faults (12 fetch, 13 load, 15 store)/software-check 18/hardware-error 19, with 24–31 and 48–63 for custom use.
Hardware Designer Notes
For a Linux-bootable hart this page plus satp IS the supervisor programming model. The delegation flow to get here: medeleg/mideleg route U/S traps directly to S-mode so M-mode firmware never sees a Linux syscall.
Minimal Linux-boot hart MUST
- Implement sstatus/sip/sie as masked windows onto the mstatus/mip/mie flops — SPP, SPIE, SIE, SUM, MXR, FS (if F), plus the trap/SRET state machines on them
- Provide stvec (Direct mode suffices: MODE WARL may pin to 0), sscratch, sepc holding all valid VAs, scause codes 0-31, and scounteren (bits may all be RO-0)
- Evaluate the S-interrupt trap condition after every sip/sie/sstatus write and SRET — a stale pending evaluation deadlocks idle loops
MAY simplify / trap-and-emulate
- Hardwire UXL (no dynamic XLEN), UBE=0, and omit SDT/SPELP without Ssdbltrp/Zicfilp
- Implement Vectored stvec later — Linux uses Direct mode
- Treat FS=Off traps as the lazy-FP-switch hook, or hardwire FS=Dirty and always save FP state
Check yourself — supervisor CSRs
1.How many extra flip-flops does sstatus cost over mstatus in a straightforward implementation?
2.S-mode runs with SUM=1. Which access to a U=1 page still fails?
3.When exactly does interrupt i trap to S-mode?
4.Multiple supervisor interrupts arrive simultaneously. Which is taken first, and where does the handler start with stvec MODE=Vectored?
5.What must be true for U-mode to read the cycle counter?