The V extension is RISC-V’s answer to a question x86 answered badly three times (SSE → AVX → AVX-512, each with its own binaries): how does one instruction set span hardware from microcontrollers to supercomputers? V’s answer is vector-length agnosticism vector length agnostic The V extension's core contract: binaries never encode VLEN. Software reads vl from vsetvli per strip-mine iteration, so the same code runs on VLEN=128 and VLEN=4096 hardware — wider machines just retire fewer iterations. defined in ch. I·31 — open in glossary — the binary never knows how wide the hardware is. Sixteen pages of this book’s largest chapter follow; this page sets up the two numbers everything else depends on.
| Constraints & consequences | |
|---|---|
| ELEN — max element width | ≥ 8, power of two. The widest element any operation produces or consumes. Standard profiles pin it further (V proper: ELEN = 64). |
| VLEN — bits per vector register | ≥ ELEN, power of two, ≤ 2^16. |
| Portability contract | Binaries written to the strip-mining discipline execute correctly on ANY conforming VLEN — but code CAN expose the parameters (vlenb is a CSR), and threads with live vector state cannot migrate across harts with different VLEN/ELEN. |
Hardware Designer Notes
The VLEN-vs-DLEN split is the fundamental vector-microarchitecture trade: long VLEN amortizes instruction overhead (fewer strip-mine iterations), narrow DLEN bounds area. Most first implementations choose VLEN = 128 or 256 with DLEN = VLEN/2 or VLEN.
Minimal Linux-boot hart MUST
- Pick VLEN and ELEN as the FIRST vector design decision — every structure downstream (register file = 32 × VLEN bits, index widths, mask geometry) derives from them
- Honor the power-of-two and VLEN ≥ ELEN rules; profiles add floors (V proper needs VLEN ≥ 128, ELEN = 64)
MAY simplify / trap-and-emulate
- Decouple datapath width (DLEN) from VLEN — a VLEN=256 register file over a 128-bit datapath simply executes two beats per instruction; VLA makes the split architecturally invisible
- Choose Zve32x/Zve64x embedded profiles (next pages) instead of full V for MCU-class cores
Check yourself — V parameters
1.What are ELEN and VLEN, and what bounds does v1.0 place on them?
2.What does vector-length-agnostic (VLA) portability promise — and what's the documented exception?