IEEE 754 binary128, structured as a pure widening of
D: FLEN grows to 128, the fmt field’s last code
(11 = Q, joining 00 S / 01 D / 10 H), and NaN-boxing goes
recursive — a single sits boxed inside a double boxed inside a
quad, upper bits all ones at each level. Every instruction is the
double-precision instruction with fmt=Q:
| Instructions & fine print | |
|---|---|
| FLQ / FSQ | LOAD-FP/STORE-FP with the Q width code; bit-transparent (non-canonical NaN payloads preserved); atomic ONLY if naturally aligned and XLEN=128 — i.e., never on today’s cores. |
| Arithmetic | FADD/FSUB/FMUL/FDIV/FSQRT/FMIN/FMAX.Q and the four fused multiply-adds, all analogous to D. |
| Integer converts | FCVT.W[U].Q, FCVT.L[U].Q (RV64-only) and reverses. |
| FP converts | FCVT.S.Q / FCVT.Q.S / FCVT.D.Q / FCVT.Q.D — the full triangle with S and D. |
| Sign-injection, compare, classify | FSGNJ[N/X].Q, FEQ/FLT/FLE.Q, FCLASS.Q — as in D. |
| FMV.X.Q / FMV.Q.X | NOT PROVIDED on RV32/RV64: no integer register holds 128 bits, so quad bit patterns travel through memory. (Reserved for a future RV128.) |
Hardware Designer Notes
Q is in this book for completeness, not for your Linux-boot core: no standard profile mandates it, the kernel never touches it, and the area of a fused 128-bit FMA rivals a small in-order core. If a customer genuinely needs it, benchmark soft-float first.
Minimal Linux-boot hart MUST
- If implementing Q in hardware: widen the f-register file to 128 bits, extend NaN-box checking one level deeper, and provide the full convert triangle
- Keep FLQ/FSQ bit-transparent — no canonicalization on the load/store path
MAY simplify / trap-and-emulate
- Skip Q entirely — the near-universal choice: a 113-bit multiplier array is ~4× a double’s area for workloads (long-double math, some HPC) that tolerate software emulation
- Note glibc on RISC-V maps long double to binary128 in SOFTWARE precisely so hardware Q remains optional
Check yourself — Q extension
1.How does a quad-precision bit pattern get from an f-register to x-registers on RV64?
2.Why is FCVT.Q.L (64-bit int → quad) unaffected by the rounding mode?
3.With Q implemented, what does a valid single-precision value look like in an f-register?