Glossary

Every term the two volumes define — 133 of them — with the chapter that introduced it. These are the same definitions behind the dotted-underline tooltips throughout the site.

133 shown

1:1 expansion rule ch. I·28: Design constraint of RVC: every 16-bit instruction maps to exactly one 32-bit base/F/D instruction, so decoders expand early and compilers may ignore C entirely. Sole semantic wrinkle: C.JAL/C.JALR write pc+2 as the link value.
accelerator ch. I·1: A non-programmable fixed-function unit, or an autonomous specialized core (often RISC-V-based), used to offload work such as I/O processing.
accumulating csr ch. I·18: A CSR that is both source and destination of an instruction but carries a dependency only from itself to itself - the FP exception flag bits (NV/DZ/OF/UF/NX), so FP ops never serialize on fflags.
amo ch. I·13: Atomic memory operation (Zaamo): atomically load to rd, apply op(loaded, rs2), store back. SWAP/ADD/AND/OR/XOR/MAX[U]/MIN[U], .W/.D; RV64 .W forms sign-extend rd. Natural alignment unless the misaligned atomicity granule PMA applies.
aq/rl bits ch. I·13: Per-atomic ordering bits: aq = acquire (no later memory ops observed before it), rl = release (not observed before earlier ops), both = sequentially consistent — scoped to the address domain (memory or I/O) the atomic touches. RCsc release consistency support.
asid ch. II·12: Address Space IDentifier: satp field tagging TLB entries per address space so context switches need no flush. Hart-local meaning; ASIDLEN discoverable by write-ones-readback (max 9 bits Sv32, 16 bits Sv39/48/57); may legally be zero bits.
atomicity axiom ch. I·18: For aligned paired LR/SC: if the LR read byte x from store s, no OTHER hart's store to x may sit between s and the SC's write in the global memory order.
byte-address invariance ch. I·2: Endianness property RISC-V mandates: a byte stored at an address is returned by a byte load from that address in ANY endianness.
c.addi16sp / c.addi4spn ch. I·28: Stack-frame idioms: C.ADDI16SP adjusts sp by +/-16-byte multiples (shares the C.LUI opcode, rd=x2); C.ADDI4SPN (CIW) computes sp + zero-extended nonzero uimm*4 into a prime register - pointers to stack slots.
cache block ch. I·20: The NAPOT-aligned unit CBO instructions operate on — uniform size across the system in CMO v1, discoverable by software (zero-block size may differ from management-block size). Identified by any physical address within it.
calling convention ch. I·2: Software contract, not architecture: x1 = return address (ra), x5 = alternate link register, x2 = stack pointer (sp). Hardware may exploit it (return-address stacks, compressed encodings assume it).
canonical nan ch. I·21: The only NaN RISC-V FP ops produce: positive sign, quiet bit set, all other significand bits clear (0x7fc00000 single). Payload propagation is not standard; FLW/FSW/FMV/FSGNJ still preserve raw bits.
cbo ch. I·20: Cache-Block Operation: the CMO subset acting on single cache blocks. Zicbom = CBO.INVAL/CLEAN/FLUSH (communicate with non-coherent agents), Zicboz = CBO.ZERO (store zeros to a whole block), Zicbop = PREFETCH.R/W/I hints. Gated per privilege mode by the xenvcfg CBIE/CBCFE/CBZE fields.
constrained lr/sc loop ch. I·13: A <=16-instruction sequential loop (LR..SC with only restricted base-I instructions between; retry branches allowed) in a region with the eventuality property. The EE must guarantee livelock freedom for it; unconstrained sequences may never succeed.
control transfer records ch. II·11: Smctr/Ssctr: a circular on-chip buffer (depth 16-256) recording qualified control transfers (source PC, target PC, type, mispredict, compressed cycle count) for low-overhead profiling. Accessed via siselect 0x200+N (logical entry 0 = youngest); configured by m/s/vsctrctl (mode enables, type filters, RASEMU call-stack mode, freeze-on-LCOFI/breakpoint); SCTRCLR wipes it.
coprocessor ch. I·1: A unit attached to a RISC-V core, mostly sequenced by the core's instruction stream, with additional architectural state and extensions and possibly limited autonomy.
core ch. I·1: A component containing an independent instruction-fetch unit; one core may support multiple harts via multithreading.
counter delegation ch. II·9: Smcdeleg/Ssccfg: with menvcfg.CDE=1, counters whose mcounteren bit is set become S-mode WRITABLE via siselect 0x40+i / sireg* (Table 25 map; 0x41 = hole, mtime is not supervisor-managed; MINH masked to 0). Adds scountinhibit as a masked mcountinhibit alias. Cuts M-mode trap latency out of perf sampling and context switches.
csr ch. I·6: Control and Status Register: one of a separate 4096-entry per-hart address space (csr specifier = instruction bits 31:20), accessed only via the atomic read-modify-write Zicsr instructions (CSRRW/S/C and immediate forms).
csr access ordering ch. I·6: A hart observes its own CSR accesses in program order (side effects visible to the next instruction). Globally, CSR accesses are weakly ordered under RVWMO and unordered vs memory accesses; FENCE covers them with CSR read = device input (I), CSR write = device output (O).
csr field modulation ch. II·2: When a write to CSR A changes the legal-value set of a field in CSR B, that field immediately takes an UNSPECIFIED value from the new legal set (even if the old value stayed legal) - unless it aliases another field, in which case it reflects the alias. Not a write: no side effects fire.
csr shadowing ch. II·2: Exposing one register at two addresses with different access classes when it is read-only at a lower privilege but read-write higher (counters: cycle 0xC00 URO vs mcycle 0xB00 MRW) - avoids trapping legal lower-priv reads under virtualization.
csr side effect ch. I·6: A consequence of a CSR read/write not determined solely by the CSR's value (spec example: read turns a light on). Standard CSRs have NO read side effects; write side effects are possible in principle. A trap caused by the value a write installed is an INDIRECT effect, not a side effect.
custom extension ch. I·1: A non-standard extension that uses only custom encoding space; a non-conforming extension is one that uses standard or reserved encodings without being standard.
cycle counter ch. I·7: Unprivileged read-only 64-bit CSR 0xC00: clock cycles executed by the CORE (not hart) since an arbitrary start. Must not advance while the core is fully clock-gated. RDCYCLE[H] pseudos read it.
d-mode ch. II·1: Debug mode: an optional above-M privilege level from the separate debug specification; reserves a few CSR addresses (only accessible in D-mode) and possibly physical address space.
division-by-zero semantics ch. I·12: No trap, ever (Table 11): quotient = all bits set (both signednesses), remainder = dividend. Signed overflow (-2^(L-1) / -1): quotient = dividend, remainder = 0. W forms sign-extend these constants.
ebreak ch. I·2: SYSTEM instruction returning control to a debugging environment; also used for semihosting via the fixed sequence slli x0,x0,0x1f; ebreak; srai x0,x0,7 (all 32-bit forms).
ecall ch. I·2: SYSTEM instruction raising a precise requested trap to the execution environment — the service-call mechanism (parameters per EEI, usually in registers).
exception ch. I·1: An unusual condition occurring at run time, associated with an instruction in the current hart (synchronous).
execution environment interface (eei) ch. I·1: The contract a RISC-V program runs against: initial state, number/type of harts and their privilege modes, memory and I/O accessibility, behavior of legal instructions, and trap handling. Examples: Linux ABI, RISC-V SBI.
fclass ch. I·21: Writes a 10-bit one-hot mask classifying rs1: -inf, -normal, -subnormal, -0, +0, +subnormal, +normal, +inf, sNaN, qNaN. Sets no flags.
fcsr ch. I·21: Floating-point control/status CSR: bits 7-5 = frm (dynamic rounding mode), bits 4-0 = fflags (accrued NV/DZ/OF/UF/NX), 31-8 reserved (read zero, ignore writes). frm and fflags are also standalone CSR addresses; FRCSR/FSRM/FSFLAGS etc. are pseudos.
fence predecessor/successor sets ch. I·2: FENCE names two subsets of {device Input, device Output, memory Reads, memory Writes}: no other hart/device may observe any successor-set operation before any predecessor-set operation.
fence.i ch. I·5: Zifencei's one instruction: orders all prior explicit memory accesses (program order, same hart) before all subsequent instruction fetches. Strictly hart-local; cross-hart code publication = writer data-FENCE + each reader FENCE.I. funct12/rs1/rd reserved (ignored).
flen ch. I·21: Width of the floating-point registers: 32 with F, 64 with D, 128 with Q. Independent of XLEN.
fri-rfi and rsw ch. I·A: The two sanctioned same-address load-load reorderings under CoRR: fri-rfi (younger load forwards from own store and performs early - returned value is still newer) and RSW (two loads reading the SAME store may perform out of order). Different-store cases stay forbidden by PPO rule 2.
fs/vs/xs ch. II·3: Extension context status in mstatus: Off/Initial/Clean/Dirty (2b each; XS read-only summary; SD = any dirty, sign bit). Off -> accessing state traps. Context switch saves only Dirty state. M and S share the fields; imprecise dirty tracking is legal.
fsgnj family ch. I·21: FSGNJ/FSGNJN/FSGNJX: rs1's bits with the sign from rs2 / its inverse / the XOR of both signs. No flags, no NaN canonicalization. With rs1=rs2 they are FMV.S / FNEG.S / FABS.S.
global mapping ch. II·12: PTE with G=1: present in every address space, so TLBs may keep one copy across ASIDs and ASID-filtered SFENCE.VMAs skip it. Marking a non-global mapping global is a software bug with unpredictable translation results.
global memory order ch. I·18: A total order over the memory operations of ALL harts in one execution. RVWMO legality = there exists a global memory order respecting preserved program order and the load-value/atomicity/progress axioms.
guest physical address ch. II·15: GPA: the intermediate address between VS-stage and G-stage translation — what the guest OS believes is physical. 2 bits wider than the VA width (34/41/50/59 bits), reported to hypervisors in htval/mtval2 shifted right by 2.
hart ch. I·1: A hardware thread: the abstract resource that autonomously fetches and executes RISC-V instructions within an execution environment; may be time-multiplexed onto physical hardware but must behave like an independent hardware thread.
high-half csrs ch. II·2: RV32 companions (timeh, mcycleh, menvcfgh...) aliasing bits 63:32 of 64-bit CSRs. Exist only when XLEN=32; their addresses are reserved on RV64 and typically raise illegal-instruction.
hint instruction ch. I·2: An encoding (mostly integer ops with rd=x0, or null-effect FENCEs) that changes no architectural state except pc/counters; implementations may ignore it or execute it as a dead operation. Never traps.
hpmcounter ch. I·7: hpmcounter3-31 (Zihpm): up to 29 unprivileged 64-bit platform-defined performance counters. Unimplemented ones may trap illegal-instruction or read constant; events/access controlled by the privileged architecture (mhpmevent, mcounteren).
hypervisor extension ch. II·15: The H extension: turns S-mode into HS-mode and adds guest modes VS/VU (virtualization bit V=1) with two-stage address translation, hypervisor CSRs (hstatus, hgatp, hedeleg…), VS shadow CSRs that substitute when V=1, HLV/HSV guest-memory instructions, and HFENCE fences. misa bit 7.
ialign ch. I·1: The instruction-address alignment constraint an implementation enforces: 32 bits in the base ISA, relaxed to 16 by extensions like C; no other values allowed.
ilen ch. I·1: The maximum instruction length an implementation supports; a multiple of IALIGN (32 bits for base-only implementations).
implicit memory access ch. I·1: A memory access an instruction performs beyond its explicit semantics — instruction fetch, and (per the EE) things like page-table walks. Side-effect-free non-excepting implicit reads may occur arbitrarily early and speculatively.
indirect csr access ch. II·5: Smcsrind/Sscsrind: a select CSR (m/s/vsiselect) routes six alias CSRs (m/s/vsireg1-6) onto extension register files - multiplying the 12-bit CSR space. Select values are their own address space (MSB = custom); siselect must hold 0..0xFFF for emulation headroom; widths follow current XLEN; unimplemented selects should trap illegal-instruction; stateen0 bit 60 gates it.
instret ch. I·7: Unprivileged read-only 64-bit CSR 0xC02: instructions retired by this hart. Synchronous-exception-causing instructions (incl. ECALL/EBREAK) do not retire and do not count.
instruction parcel ch. I·1: A 16-bit unit of instruction encoding. Instructions are one or more parcels, stored little-endian at increasing halfword addresses regardless of data-memory endianness.
instruction-fetch coherence ch. I·5: Visibility of data stores to instruction fetches. RISC-V guarantees none by default — fetches may be served from arbitrarily stale prefetched bytes until the hart executes FENCE.I (or a future mechanism).
interrupt ch. I·1: An external asynchronous event that may cause a hart to experience an unexpected transfer of control.
jvt ch. I·29: URW CSR 0x017: WARL base[XLEN-1:6] (64-byte-aligned jump-table base, virtual address) + mode[5:0] (0 = jump-table mode, others reserved). Context state - saved/restored on process switch; Smstateen-gated when present.
landing pad ch. I·34: Zicfilp forward-edge CFI: the LPAD instruction marks every valid indirect call/jump target. An indirect branch arms ELP=LP_EXPECTED; if the target isn't an LPAD (with a matching 20-bit label in x7, when labeling is used), a software-check exception fires — shrinking the ROP/JOP gadget space to landing-pad-preceded entry points.
lmul ch. I·31: Vector register group multiplier (vtype.vlmul, powers of two from 1/8 to 8): LMUL>1 gangs 2/4/8 aligned registers into one operand (VLMAX = LMUL·VLEN/SEW); fractional LMUL parks narrow data in a register fraction so mixed-width loops keep all 32 register names usable.
load value axiom ch. I·18: Each byte of a load returns the store latest in {stores earlier in global memory order, stores earlier in PROGRAM order} - the second clause architecturally legalizes store-buffer forwarding of the hart's own not-yet-global stores.
load-store architecture ch. I·2: Only loads and stores access memory; arithmetic operates solely on registers.
lwu ch. I·4: RV64I load-word-unsigned: zero-extends the loaded 32 bits. Plain LW sign-extends on RV64 (upholding the sign-extension invariant); LD/SD move full 64-bit values.
mcause ch. II·3: Interrupt bit + WLRL code. Interrupts: 1/3 SSI/MSI, 5/7 STI/MTI, 9/11 SEI/MEI, 13 LCOFI. Exceptions: 0 IAM, 1 IAF, 2 illegal, 3 breakpoint, 4/6 load/store misaligned, 5/7 load/store access fault, 8/9/11 ecall U/S/M, 12/13/15 page faults, 16 double trap, 18 software check, 19 hardware error.
mip/mie ch. II·3: Interrupt pending/enable, bit i = cause i. Trap to M iff (mode<M, or M with mstatus.MIE) AND mip[i]&mie[i] AND !mideleg[i], evaluated in bounded time. Priority MEI>MSI>MTI>SEI>SSI>STI>LCOFI. MEIP/MTIP/MSIP read-only (controller/mtimecmp/msip-mapped); SEIP read = sw-bit OR controller signal but RMW acts on the sw bit only.
misa ch. II·3: WARL CSR 0x301: MXL (RO, 1=RV32/2=RV64) + 26 extension letter bits (A-Z). Reset = maximal set. Clearing a bit disables the extension; dependency violations clear both bits (F=0,D=1 -> both 0); a write raising IALIGN with a misaligned next PC is suppressed. Zero misa = feature discovery elsewhere.
misaligned atomicity granule ch. I·13: Optional PMA (Vol II): a power-of-two granule within which misaligned AMOs/loads/stores (base + F/D/Q <=XLEN) raise no alignment exception and execute as ONE RVWMO memory operation.
mprv/mxr/sum ch. II·3: mstatus memory-privilege modifiers: MPRV = data accesses translate/protect/endian as MPP's mode (fetch unaffected; cleared by xRET to <M). MXR = loads succeed from executable-only pages. SUM = S-mode may touch U pages. MXR/SUM affect only PTE permissions, never PMA/PMP.
mstatus privilege stack ch. II·3: Per-mode two-level stacks in mstatus: xIE (global enable), xPIE (prior enable), xPP (prior privilege; MPP 2b, SPP 1b, WARL over implemented modes <= x). Trap into x from y: xPIE<-xIE, xIE<-0, xPP<-y. xRET: xIE<-xPIE, mode<-xPP, xPIE<-1, xPP<-least-privileged mode; to <M also MPRV<-0.
mtime/mtimecmp ch. II·3: Memory-mapped 64-bit platform timer: mtime = constant-frequency wall clock (shared, own clock domain); MTIP pending iff mtime >= mtimecmp (unsigned), cleared by writing mtimecmp. time CSR is a read-only shadow. RV32 write order: low=-1, high, low.
mtval ch. II·3: Trap value: faulting virtual address (fetch/load/store faults; portion address for misaligned/split cases) or faulting instruction bits on illegal-instruction (right-justified), or software-check code; 0 when uninformative. WARL; may be read-only zero platform-wide.
mtvec ch. II·3: WARL trap vector: BASE[?:2] (4-byte aligned, may be read-only) + MODE: 0 = Direct (all traps to BASE), 1 = Vectored (interrupts to BASE + 4x cause). Reset/NMI vectors are platform-defined, separate.
mulh family ch. I·12: MULH/MULHU/MULHSU return the upper XLEN bits of the 2xXLEN product (signed x signed / unsigned x unsigned / signed rs1 x unsigned rs2). Fusion idiom: MULH first, then MUL, same operand order, rdh distinct from sources.
multi-copy atomicity ch. I·A: RVWMO/RVTSO property: a store visible to any OTHER hart is conceptually visible to all harts. Own-store-buffer forwarding is the only early visibility allowed; no inter-hart forwarding before global visibility. Keeps fences thread-local (non-cumulative).
nan-boxing ch. I·22: Storing a valid narrower n-bit FP value in the low n bits of an FLEN-bit register with ALL upper bits = 1 (reads as a negative qNaN at wider widths). Transfers box on write and export raw low bits without checking; all other narrower ops check the box and substitute the n-bit canonical NaN when invalid.
natural alignment ch. I·2: An access is naturally aligned when its effective address is divisible by the access size in bytes. Naturally aligned loads/stores never raise address-misaligned exceptions and are atomic; misaligned behavior is EEI-defined.
operational vs axiomatic model ch. I·B: Two equivalent RVWMO formalizations: axiomatic (Alloy/herd - predicates over complete candidate executions) and operational (abstract state machine with explicit out-of-order/speculative execution, built incrementally). Intended extensionally identical; the known mixed-size RSW discrepancy is the exception - follow the stricter operational verdict.
pma ch. II·3: Physical Memory Attributes: per-region fixed hardware properties (main-memory vs I/O, access widths, atomicity levels AMONone..AMOArithmetic, reservability RsrvNone/NonEventual/Eventual, misaligned granule, ordering channels, coherence/cacheability, idempotency) checked by a dedicated PMA checker; violations = precise access faults where possible.
pmp ch. II·3: Physical Memory Protection: up to 64 M-mode-only WARL entries (8-bit cfg: R/W/X, A = OFF/TOR/NA4/NAPOT, L = lock+apply-to-M; pmpaddr = PA bits 55:2). Lowest-numbered matching entry wins and must cover ALL bytes; no match: M succeeds, S/U fails. Grain 2^(G+2); NAPOT size in trailing ones. Changes need SFENCE.VMA.
pointer masking ch. II·18: RV64 family (Ssnpm/Smnpm/Smmpm): the top PMLEN bits (7 or 16) of every explicit-access effective address are ignored — sign-extended away for virtual addresses, zeroed for physical — so software like HWASAN can keep tags there. Per-mode enables live in the next-higher mode's envcfg PMM field; MXR suppresses it; implicit accesses and fences are never masked.
preserved program order ch. I·18: The subset of each hart's program order that the global memory order must respect - 13 rules: overlapping-address (1-3), explicit synchronization FENCE/acquire/release/RCsc/pairing (4-8), syntactic address/data/control dependencies (9-11), pipeline dependencies (12-13).
prime registers ch. I·28: The 3-bit rs1'/rs2'/rd' fields of CIW/CL/CS/CA/CB formats: x8-x15 (s0,s1,a0-a5) and f8-f15 - the ABI's hot registers, made contiguous specifically for cheap decompression (value = field + 8).
privilege mode ch. II·1: The mode a hart currently runs at: U=00, S=01, M=11 (10 reserved), encoded in CSR state but not directly readable. M is mandatory and fully trusted; legal combos are M, M+U, M+S+U (the Unix/Linux configuration).
program counter (pc) ch. I·2: The one additional unprivileged register besides x0-x31: holds the address of the current instruction.
progress axiom ch. I·18: No memory operation may be preceded by an infinite sequence of operations in the global memory order - stores eventually become visible; spinloops eventually see updates.
pseudoinstruction ch. I·2: An assembler alias for a real encoding: MV=ADDI rd,rs,0; NOT=XORI rd,rs,-1; SEQZ=SLTIU rd,rs,1; SNEZ=SLTU rd,x0,rs; J=JAL x0; RET=JALR x0,x1,0; NOP=ADDI x0,x0,0.
pte ch. II·12: Page Table Entry: V validity, R/W/X permissions (000 = pointer to next level; W without R reserved), U user-accessible, G global, A accessed, D dirty, RSW software bits, PPN. RV64 formats add N (Svnapot) and PBMT (Svpbmt) in the high bits.
push/pop idempotency ch. I·29: cm.push/pop sequences may split/reorder/repeat their byte accesses and are RE-EXECUTED from scratch after any mid-sequence trap (xEPC = the instruction's own PC) - so sp must point to idempotent memory; cores may PMA-detect and access-fault otherwise.
rcpc/rcsc annotation ch. I·18: Acquire/release annotation strengths: RCsc (sequentially-consistent sync ops) is what aq/rl on LR/SC/AMO produce; RCpc (processor-consistent) currently arises only from Ztso's implicit annotations. PPO rules 5-7 define their exact force.
reservation set ch. I·13: Bytes registered by LR (superset of the addressed word/doubleword). SC succeeds only if the reservation is valid, covers the written bytes, and no conflicting store/SC intervened. One reservation per hart; ANY SC invalidates it.
reserved instruction ch. I·2: An encoding saved for future standard use; decoding one is UNSPECIFIED behavior (a platform may require illegal-instruction traps).
reset state ch. II·3: Mode=M, MIE=MPRV=0, MBE=0, misa maximal, no reservation, pc=reset vector, mcause=reset cause, PMP A/L=0, mnstatus.NMIE=0, mseccfg MML/MMWP/RLB/MLPE=0; no WARL field illegal; everything else UNSPECIFIED.
return-address stack (ras) ch. I·2: Predictor structure for returns. RISC-V encodes push/pop hints implicitly: JAL/JALR with rd or rs1 in {x1,x5} (Table 3, Vol I p. 31), including pop-then-push for coroutines.
rf/co/fr edges ch. I·A: Litmus-diagram relations: rf = reads-from (store to the loads returning its value), co = coherence (total order of stores per address), fr = from-reads (load to co-successors of its source store). With ppo/fence/addr/ctrl/data they constrain the global memory order.
rmem and sail ch. I·B: rmem (github.com/rems-project/rmem): the exploration tool embedding the operational model with Sail-defined RV64IA instruction semantics; runs litmus tests and small ELFs exhaustively, pseudorandomly, or interactively (web + CLI). Sail is the ISA-description language; sail-riscv is the golden ISA model.
rounding mode ch. I·21: RNE 000 (nearest-even), RTZ 001, RDN 010, RUP 011, RMM 100 (nearest-max-magnitude), 111 DYN in an instruction's rm field = use frm. 101/110 (and DYN inside frm) reserved - reserved-rm behavior is reserved (trapping legal).
rvc ch. I·28: The compressed 16-bit instruction set (C extension on any base). Every RVC instruction expands 1:1 to a single base/F/D 32-bit instruction at decode; IALIGN becomes 16 and instruction-address-misaligned exceptions cease to exist.
rvc quadrant map ch. I·28: op[1:0] selects the quadrant: 00 (loads/stores + ADDI4SPN), 01 (immediates/jumps/branches/CA-arith), 10 (SLLI, SP-relative loads/stores, JR/MV/ADD/EBREAK); 11 = wider-than-16-bit instructions.
satp ch. II·12: Supervisor Address Translation and Protection CSR: MODE (Bare/Sv32 on RV32; Bare/Sv39/Sv48/Sv57 on RV64) + ASID + root-page-table PPN in one register so a context switch swaps address space and ASID atomically. Writing it does NOT flush TLBs — that's SFENCE.VMA's job.
sbi/see ch. II·1: Supervisor Binary Interface / Supervisor Execution Environment: the OS-to-firmware contract (user+supervisor ISA plus SBI calls). One SBI lets one OS binary run on a bootloader SEE, a hypervisor VM, or a simulator. Linux's SEE is typically OpenSBI in M-mode.
sew ch. I·31: Selected Element Width (vtype.vsew): the dynamic element size (8/16/32/64) a vector register is currently viewed as. Widening ops produce 2·SEW results in 2·LMUL groups; ELEN caps the maximum.
sfence.vma ch. II·12: Supervisor memory-management fence: orders prior stores before subsequent implicit page-table reads and invalidates address-translation cache entries, filtered by rs1 (one VA) and rs2 (one ASID) — x0 meaning 'all'. Local-hart only; cross-hart shootdown = fence + IPI + remote SFENCE.VMA.
shadow stack ch. I·34: Zicfiss backward-edge CFI: a second, MMU-protected stack (pointer in ssp) holding shadow copies of return addresses. Non-leaf prologues SSPUSH the link register; epilogues SSPOPCHK it against the regular stack's copy, faulting on mismatch — detecting return-address overwrites (ROP). Instructions are MOP-encoded so non-CFI cores run them as no-ops.
shamt ch. I·2: Shift amount field: constant shifts encode the amount in imm[4:0] (RV32) with the right-shift type selected by instruction bit 30 (SRLI vs SRAI).
sign-extension invariant ch. I·4: RV64 convention: every 32-bit value is held sign-extended in its 64-bit register (bits 63:32 = bit 31), even for unsigned values. W-suffix instructions re-establish it after 32-bit adds/subs/shifts; conversions signed<->unsigned-32 and signed 32->64 become no-ops.
signaling vs quiet comparison ch. I·21: FLT/FLE are signaling (NV on ANY NaN input); FEQ is quiet (NV only on sNaN). All three return 0 when either operand is NaN.
single-copy atomic ch. I·18: Property of every RVWMO memory operation: it can never be observed partially complete by anyone.
smcntrpmf ch. II·7: Privilege-mode filtering for cycle/instret via mcyclecfg (0x321) / minstretcfg (0x322): MINH/SINH/UINH/VSINH/VUINH inhibit counting per mode (Sscofpmf register format, OF bit dead). instret: retire-mode gated; xRET counts by originating mode - so a faulting user instruction counts exactly once. Removes kernel noise and a timing side channel from user self-profiling.
smepmp ch. II·6: PMP enhancements: mseccfg.MML (sticky) reinterprets pmpcfg.L as rule ownership (L=1 M-only, L=0 S/U-only, RW=01 & LRWX=1111 shared regions) and restricts M-mode execution to M-rules; MMWP (sticky) denies no-match M accesses; RLB temporarily unlocks locked rules. Discovery via BootROM setting the sticky bits.
smrnmi ch. II·8: Resumable NMIs: parallel save set mnscratch/mnepc/mncause/mnstatus (MNPP/MNPV/MNPELP/NMIE) + MNRET. RNMI inputs outrank everything and ignore MIE; NMIE resets 0, is software-settable but never clearable (no nesting); NMIE=0 disables all interrupts, suppresses MPRV, and redirects M-mode exceptions to a separate RNMI exception vector.
stateen mechanism ch. II·4: Smstateen/Ssstateen: mstateen0-3 / hstateen0-3 / sstateen0-3 gate LESS-privileged access to small extensions' state (jvt, Zfinx fcsr, AIA CSRs, custom state...), closing covert channels the OS doesn't context-switch. Zero cascades down as read-only-zero; blocked access = illegal/virtual-instruction; bit 63 gates the next level's stateen itself (emulation recursion).
strip mining ch. I·31: The V-extension loop idiom: each iteration asks vsetvli for vl = min(remaining, VLMAX), processes vl elements, advances pointers by vl, repeats — handling any application vector length without remainder loops.
syntactic dependency ch. I·18: j depends on i when a source register of j traces (possibly through carrying instructions) to a destination register of i. Address/data/control flavors order memory ops via PPO 9-11. Loads, JALR, LR/SC/AMOs carry NO src->dst dependency; successful SC's rd IS a destination.
table jump ch. I·29: Zcmt's cm.jt/cm.jalt (index<32 = jt, else jalt with ra link): fetch entry XLEN wide at jvt.base + index*(XLEN/8) - a second IMPLICIT INSTRUCTION FETCH (execute permission, data endianness, fence.i after table writes), then jump to entry & ~1. Faults report the table-jump PC in xEPC.
time counter ch. I·7: Unprivileged read-only 64-bit CSR 0xC01: wall-clock ticks since an arbitrary start. EE publishes tick period/accuracy; all harts must appear synchronized within one tick, monotonically nondecreasing.
tininess after rounding ch. I·21: RISC-V detects underflow tininess AFTER rounding (fewer spurious underflow flags) - an IEEE-allowed choice your FPU's UF detector must match.
trap ch. I·1: The transfer of control to a trap handler caused by an exception or an interrupt. From inside an execution environment a trap is contained, requested, invisible, or fatal.
trap delegation ch. II·3: medeleg/mideleg bit i sends trap i occurring in S/U-mode to the S-mode handler (scause/sepc/stval/SPP/SPIE/SIE written; m* untouched). Traps never delegate downward from M-mode occurrences; delegated interrupts are masked at M. medeleg[11] and [16] read-only zero.
two-stage address translation ch. II·15: Active whenever V=1: a guest virtual address is translated by VS-stage (vsatp, guest's own page tables) to a guest physical address, then by G-stage (hgatp, hypervisor's tables, Sv39x4-style with 2 extra bits and a 16 KiB root) to a supervisor physical address. Even the VS-stage page-table reads themselves go through G-stage.
unspecified ch. I·1: A behavior or value the architecture intentionally leaves unconstrained; extensions, platform standards, or implementations may constrain it further.
urlist/spimm ch. I·29: CMPP-format fields of cm.push/pop[ret[z]]: urlist encodes the saved-register list {ra[, s0-sN]} (12 valid lists; {ra,s0-s10} invalid - use s11); spimm adds 0-3 extra 16-byte stack-pointer increments beyond the register storage.
vector length agnostic ch. I·31: The V extension's core contract: binaries never encode VLEN. Software reads vl from vsetvli per strip-mine iteration, so the same code runs on VLEN=128 and VLEN=4096 hardware — wider machines just retire fewer iterations.
vertical vs horizontal trap ch. II·1: Vertical = trap to a higher privilege mode (the hardware primitive); horizontal = handled at the same mode, implementable as a vertical trap that returns control to a less-privileged handler (what delegation automates).
vmid ch. II·15: Virtual Machine IDentifier in hgatp: tags G-stage (and combined) TLB entries per guest so world switches need no flush, and scopes HFENCE.GVMA. Up to 7 bits (Sv32x4) or 14 bits (Sv39/48/57x4); discovery by write-ones-readback.
w-suffix instruction ch. I·4: RV64I-only 32-bit operate variants (ADDIW, ADDW, SUBW, SLLIW/SRLIW/SRAIW, SLLW/SRLW/SRAW) under opcodes OP-IMM-32/OP-32: ignore upper input bits, compute a 32-bit result, sign-extend to 64. SEXT.W = ADDIW rd,rs,0.
warl ch. II·2: Write Any, Read Legal: any write accepted (never traps); reads always return a legal value, deterministic in the written value and hart state. Discovery = write desired value, read back. The workhorse behavior of misa, mtvec, satp, pmpaddr...
wfi ch. II·3: Wait For Interrupt: may stall until a locally-enabled interrupt is pending at ANY privilege - ignoring global enables and delegation; may be a NOP; wake without trap resumes at pc+4; a taken interrupt traps on the FOLLOWING instruction. mstatus.TW=1 makes <M-mode WFI trap after a bounded timeout.
wlrl ch. II·2: Write/Read Only Legal: software must write legal values. Illegal writes MAY raise illegal-instruction, or store arbitrary-but-deterministic state; hardware needs only enough bits for supported values but must read back complete encodings.
word ch. I·1: 32 bits (4 bytes) in RISC-V terminology, regardless of XLEN; halfword = 16 bits, doubleword = 64, quadword = 128.
wpri ch. II·2: Reserved Writes Preserve, Reads Ignore: reserved whole fields. Software ignores reads and preserves on writes; unimplemented fields must be read-only zero.
write subsumption ch. I·A: Eliding the earlier of two back-to-back same-address writes. Legal ONLY when model-invisible: subsuming a store that carries a dependency (Table 92) would break a required ordering chain - forbidden. Silent stores and value-unchanged AMOs are still architecturally stores.
x0 (zero register) ch. I·2: Register x0 is hardwired to all-zero bits: writes are discarded, reads return 0. Many encodings with rd=x0 are repurposed as HINTs; loads to x0 still raise exceptions and side effects.
xlen ch. I·1: The width in bits of an integer register (32 for RV32, 64 for RV64); also sizes the byte-addressable address space (2^XLEN, circular).
zc* taxonomy ch. I·29: Zca = C minus FP loads/stores; Zcf (RV32+F) / Zcd (D) = the compressed FP load/store subsets; C = Zca[+Zcf][+Zcd]. Zcb = simple 16-bit extras (gated on M/Zbb); Zcmp = push/pop; Zcmt = table jumps; Zce = the microcontroller bundle. Zcmp/Zcmt reuse c.fsdsp encodings and are INCOMPATIBLE with Zcd.
zmmul ch. I·12: The multiplication-only subset of M (MUL/MULH/MULHU/MULHSU/MULW, identical encodings; M implies Zmmul) — for divider-less implementations like FPGA soft cores.