3.1.6mstatus: The Hart Operating-State Register

One register tracks and controls the hart’s entire operating state: privilege/interrupt stacks, memory-privilege modifiers, endianness, virtualization traps, and extension-context dirtiness. sstatus is a masked view of the same storage. (The priv PDF’s mstatus figures are among its missing diagrams — the layout below is reconstructed from the field descriptions; RV32 splits the high fields into mstatush.)

The privilege & interrupt-enable stack

The two-level stack mstatus privilege stack Per-mode two-level stacks in mstatus: xIE (global enable), xPIE (prior enable), xPP (prior privilege; MPP 2b, SPP 1b, WARL over implemented modes <= x). Trap into x from y: xPIE<-xIE, xIE<-0, xPP<-y. xRET: xIE<-xPIE, mode<-xPP, xPIE<-1, xPP<-least-privileged mode; to <M also MPRV<-0. defined in ch. II·3 — open in glossary per interrupt-capable mode is the trap mechanism’s heart:

• Taking a trap from mode y into mode x: xPIE ← xIE; xIE ← 0; xPP ← y (plus mepc/mcause/mtval — next pages).
• xRET: xIE ← xPIE; mode ← xPP; xPIE ← 1; xPP ← U (least privileged implemented mode); if the destination is below M, also MPRV ← 0.
• Global-enable geometry: running in mode x, interrupts for modes below x are always off, for modes above x always on — xIE matters only in mode x itself. The low-bit placement of MIE/SIE lets one csrci/csrsi toggle them atomically.

Memory-privilege modifiers & extension context

MPRV/MXR/SUM mprv/mxr/sum mstatus memory-privilege modifiers: MPRV = data accesses translate/protect/endian as MPP's mode (fetch unaffected; cleared by xRET to <M). MXR = loads succeed from executable-only pages. SUM = S-mode may touch U pages. MXR/SUM affect only PTE permissions, never PMA/PMP. defined in ch. II·3 — open in glossary exist to make M-mode emulation and kernel-to-user copies efficient: MPRV redirects data accesses through MPP’s translation (the firmware misaligned-access emulator’s tool), MXR reads execute-only pages, SUM opens U pages to S-mode (Linux sets it around copy_{to,from}_user).

The FS/VS/XS fs/vs/xs Extension context status in mstatus: Off/Initial/Clean/Dirty (2b each; XS read-only summary; SD = any dirty, sign bit). Off -> accessing state traps. Context switch saves only Dirty state. M and S share the fields; imprecise dirty tracking is legal. defined in ch. II·3 — open in glossary machinery drives lazy context switching:

M and S share these fields — M-mode firmware must be conservative with state it touches. Setting FS=Off preserves the FP contents; only access legality changes.

Endianness, virtualization traps, double-trap

Data endianness is per-mode (MBE/SBE/UBE; fetch always LE); implicit page-table accesses follow SBE, so flipping it demands an SFENCE.VMA. The TVM/TW/TSR trio are the classic-virtualization intercepts (shadow paging, idle-scheduling, H-emulation). And Smdbltrp’s MDT bit turns the fragile early-handler window into defined behavior: trap-while-MDT=1 escalates to the RNMI handler (Smrnmi, NMIE=1) or parks the hart in the critical-error state rather than corrupting saved state.