FCLASS.S fclass Writes a 10-bit one-hot mask classifying rs1: -inf, -normal, -subnormal, -0, +0, +subnormal, +normal, +inf, sNaN, qNaN. Sets no flags. defined in ch. I·21 — open in glossary inspects an f-register and writes a 10-bit one-hot mask into an integer register — exactly one bit set, no exception flags touched, rounding irrelevant. It’s the tool math libraries use to branch on value categories without risking NaN signaling.
| rs1 is… | Field-pattern decode | |
|---|---|---|
| bit 0 | −∞ | sign=1, exp=max, sig=0 |
| bit 1 | negative normal | sign=1, 0 < exp < max |
| bit 2 | negative subnormal | sign=1, exp=0, sig≠0 |
| bit 3 | −0 | sign=1, exp=0, sig=0 |
| bit 4 | +0 | sign=0, exp=0, sig=0 |
| bit 5 | positive subnormal | sign=0, exp=0, sig≠0 |
| bit 6 | positive normal | sign=0, 0 < exp < max |
| bit 7 | +∞ | sign=0, exp=max, sig=0 |
| bit 8 | signaling NaN | exp=max, sig≠0, quiet bit clear |
| bit 9 | quiet NaN | exp=max, sig≠0, quiet bit set |
Ten classes: eight on the extended number line (sign-split), two NaN classes off it.
FCLASS is encoded under OP-FP with funct5 = FCLASS, rm fixed at 001,
rs2 = 0 — and it never sets flags, even for signaling NaN inputs.
Hardware Designer Notes
FCLASS is nearly free: the special-case detectors your FPU already needs (zero, subnormal, ∞, NaN, quiet bit) ARE the classify unit — route them to a 10-bit one-hot writeback and you’re done. If you recode values internally, classify from the recoded form carefully: the sNaN/qNaN distinction must survive recoding.
Minimal Linux-boot hart MUST
- One-hot output, exactly one bit set, bits 31:10 zero (RV64: 63:10)
- No fflags updates on any input, sNaN included
MAY simplify / trap-and-emulate
- Share the classify logic with the FPU front-end — every FP op already decodes these patterns for special-case handling
Check yourself — FCLASS
1.FCLASS.S of −0.0 writes what to rd?
2.Does FCLASS.S of a signaling NaN set the invalid flag?
3.Which classes can a hardware classify unit derive purely from exponent/significand field patterns?