Traps mid-vector
A trap during a vector instruction writes *epc with the instruction address and vstart with the faulting element index — resumption re-enters the same instruction mid-flight. Precise vector traps require the classic two conditions across instructions, plus: results below vstart committed, and results at/after vstart unchanged — except that later elements may have been updated if re-execution from vstart overwrites them correctly (idempotent restart). Vector stores may have dirtied idempotent memory past the fault; never non-idempotent regions. Overlap rules from the formats page exist exactly to keep restart legal. Imprecise traps (report-and-terminate), a precise/imprecise mode bit, and swappable-microstate traps are all sketched but not defined in the current standard.
The extension family
| Min VLEN | Element support | |
|---|---|---|
| Zve32x | 32 | Integer only, EEW 8/16/32 (ELEN=32). Needs Zicsr. |
| Zve32f | 32 | + FP32 (requires F). |
| Zve64x | 64 | Integer to EEW 64 (ELEN=64). |
| Zve64f | 64 | + FP32 (requires F). |
| Zve64d | 64 | + FP64 (requires D). |
| V (the application profile) | 128 | Everything: EEW 8-64, FP32+FP64, requires F and D. |
Element groups (§31.19) round out the chapter: a fixed-width cluster of elements treated as one logical operand (EGW bits, EGS elements), independent of SEW — the plumbing that lets the vector-crypto extensions handle 128-bit AES blocks and 256-bit SHA states as units, with vl constrained to EGS multiples. §31.20 is the OP-V funct6 listing table — the compact map of every encoding this chapter defined.
Hardware Designer Notes
The precise-trap machinery is the hidden tax of vector Linux: every demand-paged vle needs element-granular fault attribution and mid-instruction restart. Budget it with the LSU, not as an afterthought — retrofitting vstart resumption into a whole-instruction-retry design is a redesign.
Minimal Linux-boot hart MUST
- Implement precise vector traps with vstart writeback for a Linux-class core — demand paging on vector loads/stores depends on it
- Guarantee eventual forward progress for the vstart element (no livelock between fault and re-execution)
- Meet the full V floor (VLEN ≥ 128, ELEN = 64, F+D) if targeting RVA23
MAY simplify / trap-and-emulate
- Choose a Zve profile for MCU-class designs — Zve32x is a genuinely small vector unit
- Advertise larger Zvl*b strings when your VLEN exceeds the floor (software can then assume it)
Check yourself — traps & sub-extensions
1.What do the four precise-vector-trap requirements permit that classic precise exceptions wouldn't?
2.Which vector configuration does a Linux-class application processor need — V or a Zve profile?
3.What are vector element groups (§31.19) for?