29.12.3-10Zcb: The Simple Code-Size Instructions

Part I Linux boot: recommended Vol. I (Unprivileged) pp. 175–182 · ~3 min read

Zcb fills gaps the original C extension left: sub-word memory accesses, sub-word extends, bitwise not, and a compressed multiply. Every one is a 1:1 expansion of an existing 32-bit instruction, prime-registers-only, in previously reserved encoding space — pure decoder work, no conflicts, implementable on any core whose parent extensions exist.

Sub-word loads and stores (CLB/CSB/CLH/CSH formats)

1000001510rs1′97uimm[0|1]65rd′420010c.lbu (CLB)
Click a field for its role.
1000011510rs1′97funct16uimm[1]5rd′420010c.lh/c.lhu (CLH)
Click a field for its role.

c.sb/c.sh mirror the loads (CSB/CSH, rs2′ as data). All offsets are zero-extended; all expand to the obvious base LB/LBU/LH/LHU/SB/SH.

Unary operations (CU format) and c.mul

The CU format packs single-operand ops into funct5 space with rd′ = rs1′ (“rsd′” — destructive):

Zcb instruction catalog with prerequisite gates
Expands toRequires
c.lbu / c.lhu / c.lhlbu/lhu/lh rd′, uimm(rs1′)Zca only
c.sb / c.shsb/sh rs2′, uimm(rs1′)Zca only
c.zext.bandi rsd′, rsd′, 0xffZca only
c.sext.b / c.zext.h / c.sext.hsext.b / zext.h / sext.h rsd′Zbb
c.zext.w (RV64)add.uw rsd′, rsd′, zeroZba
c.notxori rsd′, rsd′, −1Zca only
c.mulmul rsd′, rsd′, rs2′M or Zmmul
(c.sext.w)pseudo for c.addiw rd, 0RV64 — already existed in C
Dotted-underlined cells have explanations — click one.

Hardware Designer Notes

Zcb is the cheapest code-size win in the Zc* family: a handful of expander rows and nothing else. If your decode is table-driven, the whole extension is data. Watch only the two encoding quirks — the swapped uimm bits in CLB/CSB and the funct1-in-bit-6 of CLH/CSH — both are transcription-error magnets in decoder tables.

Minimal Linux-boot hart MUST

  • Decode the CLH/CSH funct1 bit (signed/unsigned select) — the offset bit order in CLB/CSB is swapped (uimm[1]=enc[5])
  • Implement each instruction exactly when its parent extension is present

MAY simplify / trap-and-emulate

  • Adopt Zcb on an RV64GC Linux core freely — reserved-space encodings, zero conflicts, ~11 expander entries

Check yourself — Zcb

1.Why do c.lbu/c.sb get 2-bit offsets while c.lh/c.lhu/c.sh get only 1 usable bit?

2.Which Zcb instructions can a bare RV64 Zca+M core implement without any B-extension support?

3.What does c.mul rsd', rs2' compute?

3 questions