5.7.1 The academic lineage
A few highlights from the vast relaxed-consistency literature, in sequence:
- Dubois et al. — weak ordering weak ordering Dubois et al.'s pioneering relaxed model, later generalized by SC for DRF. defined in Chapter 5 — open in glossary , among the first relaxed models developed.
- Adve and Hill — generalized weak ordering to the order strictly necessary for programmers with “SC for DRF”.
- Gharachorloo et al. — developed release consistency, plus “proper labeling” (viewable as a generalization of SC for DRF) and RCpc, a variant whose synchronization operations follow TSO.
- Adve and Gharachorloo — the seminal mid-1990s memory model tutorial summarizing the state of the art.
- Meixner and Sorin — to the book’s knowledge, the first to prove correct a relaxed model realized by separating cores from a cache-coherent memory system with a rule-governed reorder unit.
5.7.2 Commercial models
Besides Power, the commercial relaxed models the book surveys — compactly:
| Model | Total memory order? | Notable traits | Status |
|---|---|---|---|
| Alpha | Yes (like XC) | Did not order dependent loads — not even address dependencies | Largely defunct; lives on in Linux |
| SPARC RMO | Yes (like XC) | OS may select TSO / PSO / RMO | All current SPARCs run TSO anyway |
| ARMv7 | Apparently not (Power-like) | Data memory barrier (all accesses or stores-only), instruction sync barrier à la ISYNC, I/O fences | Superseded by ARMv8 |
| ARMv8 | Yes — multi-copy atomic | ACQUIRE/RELEASE-annotated loads and stores; similar in spirit to RVWMO (which it predates) | Current |
Two smaller notes complete the survey. SPARC’s model menu is legal to ignore: since TSO is strictly stronger than PSO and RMO, a TSO machine is automatically a valid implementation of both — it just never uses their extra latitude. And ARM’s story is one of strengthening: ARMv7’s Power-like looseness gave way to ARMv8’s multi-copy atomic, total-order model with acquire/release annotations — evidence that write atomicity write atomicity A store becomes logically visible to all other cores at once (its own core may see it early); a.k.a. store atomicity or multi-copy atomicity. defined in Chapter 5 — open in glossary earns its keep in practice.
Check yourself
1.Trace the academic lineage of relaxed models. Which chain is right?
2.Alpha is largely defunct. Why does the book still care about it?
3.SPARC lets the OS choose among TSO, PSO, and RMO — yet every current SPARC implementation runs TSO in all cases. Why is that legal?
4.What changed between ARMv7 and ARMv8's memory models?