1.6What This Primer Does Not Do

Scope: a primer, by design

This book is a primer — the authors size it at roughly ten 75-minute graduate lectures, one per chapter from 2 through 11. Keeping it that small means drawing sharp boundaries. Four neighboring topics are deliberately left out:

• Synchronization. Coherence makes caches invisible; consistency makes shared memory behave like a single memory module. Even so, real programs need locks, barriers, and other synchronization techniques to be useful — correct memory is the foundation, not the coordination. That layer has its own Synthesis Lecture (Scott, Shared-Memory Synchronization).
• Commercial relaxed consistency models in full. The subtleties of the ARM, PowerPC, and RISC-V memory models are out of scope — though the primer does describe which mechanisms those architectures provide to enforce ordering, and Chapter 5 works through RISC-V (RVWMO) and IBM Power case studies.
• Parallel programming. No programming models, methodologies, or tools.
• Consistency in distributed systems. Everything here concerns consistency within a shared-memory multicore. Consistency models for general distributed systems — replicated databases, quorum protocols — live in their own literature (the Database Replication and Quorum Systems lectures).

A useful way to hold the scope in one sentence: this primer is about what the hardware of a single shared-memory machine guarantees about loads and stores, and how it delivers that guarantee — everything above (programming with it) and beyond (distributing it) is someone else’s book.

With the map drawn — consistency in chapters 3–5, coherence in 6–9, heterogeneous systems in 10, specification and validation in 11 — the real work starts next chapter with the coherence basics needed to understand how consistency models interact with caches.