2.1Baseline System Model

Just enough coherence

Chapter 2’s job is to introduce enough about cache coherence cache coherence Making caches functionally invisible by propagating one processor's writes to other processors' caches; a means of supporting a consistency model, not a correctness definition itself. defined in Chapter 1 — open in glossary to understand how consistency models interact with caches — not to design protocols (that’s chapters 6–9). It proceeds in three moves: fix a system model (§2.1), show how incoherence can possibly arise (§2.2), define the coherence interface (§2.3), and then pin down coherence precisely through its invariants (§2.4). Throughout, the strategy is deliberate minimalism: the simplest system model sufficient to illustrate the real issues, with complications deferred to Chapter 9.

The model

The baseline is a single multicore processor chip plus off-chip main memory:

Its parts, and the properties that matter later:

• Cores — multiple, each single-threaded (multithreaded cores raise extra issues; recall pop-quiz question 4).
• Private data caches — one per core, accessed with physical addresses, write-back. Terminology convention: from here on, “cache” means a core’s private data cache — never the LLC. Each cache has a cache controller, the future protocol actor.
• Interconnection network — connects the cache controllers to the LLC.
• Last-level cache (LLC) last-level cache (llc) Shared, memory-side cache logically in front of memory; reduces latency and increases effective bandwidth, acts as the memory controller, and adds no extra coherence level. defined in Chapter 2 — open in glossary — shared by all cores, but logically a memory-side cache: it sits in front of memory to reduce average memory latency and increase effective memory bandwidth, and it serves as the on-chip memory controller. Because it holds data on behalf of memory rather than any core, it does not introduce another level of coherence issues.

What the baseline leaves out

All of these are common in real systems, and all are omitted here because they add complexity without changing the fundamental story — Chapter 9 brings them back:

instruction caches · multi-level private caches · caches shared among some (not all) cores · virtually addressed caches · TLBs · coherent DMA · multiple multicore chips.

Keep this list in mind: several pop-quiz traps (like coherent TLBs) live in exactly the gap between the baseline model and Chapter 9’s realistic ones.