A real machine that does all of it
The MIPS R10000 (1996) is the book’s venerable-but-clean commercial example of a speculative microprocessor implementing SC in cooperation with a cache-coherent memory hierarchy. The relevant specs: a four-way superscalar RISC core with branch prediction and out-of-order execution; writeback L1 instruction and data caches; a private interface to an off-chip unified L2.
Figure 3.7 (recreated): the system interface bus supports cache coherence for up to four processors.
To scale beyond four processors, architects built systems like the SGI Origin 2000 (a §8.8.1 case study): a directory coherence protocol connects R10000s via the system bus and a specialized Hub chip. Either way, the core sees one coherent memory system that happens to be partly on-chip and partly off-chip.
The address queue and the eviction squash
Everything SC-relevant happens around one structure. Step through it:
1 / 5Speculative issue into the address queue
The R10000 issues (speculative) loads and stores in program order into an address queue. A load may EXECUTE early: it obtains a speculative value from the last older store to the same address in the queue, or — if none — from the data cache.
In prose: the core issues speculative loads and stores in program order into an address queue. A load may execute early, taking its value from the last older same-address store in the queue or else the data cache. Loads and stores commit in program order; a store commits only when its L1 block is in state M, writing its value atomically with commit. The guard: eviction of any block whose address sits in the queue — coherence invalidation or plain replacement — squashes the matching load and all younger instructions, which re-execute.
So when a load finally commits, its block was continuously cached from execution to commit, and it must return the same value as if it executed at commit — the cache-residency verification of §3.8 in commercial silicon. With stores writing at commit and loads as-if-at-commit, the R10000 logically presents loads and stores in program order to the coherent memory system — exactly §3.7’s recipe — and therefore implements SC.
Check yourself
1.Where does an R10000 load obtain its (speculative) value when it executes?
2.What events squash a load waiting in the R10000's address queue?
3.Why does the eviction-squash rule guarantee a committed load's value is correct?
4.Putting it together: why is the R10000 sequentially consistent?