Coherence as an abstract interface
Informally, a coherence protocol must ensure that writes are made visible to all processors. To say this precisely, the book looks at coherence through the abstract interface it exposes. The coherence interface coherence interface The boundary between pipeline and coherence protocol: read-request(location)→value and write-request(location, value)→ack. defined in Chapter 2 — open in glossary between the processor pipelines and the coherence subsystem has exactly two methods:
- read-request(memory location) → returns a value;
- write-request(memory location, value) → returns an acknowledgment.
Figure 2.2 (recreated): the pipeline-coherence interface. Everything below the line is “the coherence box.”
Many coherence protocols exist; the book classifies them by the nature of this interface — specifically, whether coherence is cleanly separated from the consistency model or entangled with it. This makes precise the two classes previewed in §1.2.
The two categories
Consistency-agnostic consistency-agnostic coherence Coherence in which a write returns only after being made visible to all cores; presents the illusion of an atomic memory, independent of the consistency model. defined in Chapter 2 — open in glossary
- A write returns only after it is visible to all cores — synchronous propagation.
- The interface is identical to an atomic memory with no caches: it’s as if the box contained only the memory.
- Separation of concerns: coherence hides the caches; the pipeline alone enforces the consistency model’s orderings.
- The focus of chapters 6–9 (and the rest of this chapter).
Consistency-directed consistency-directed coherence Coherence in which writes propagate asynchronously but the order writes become visible must obey the consistency model; the newer GPU-era category. defined in Chapter 2 — open in glossary
- Writes propagate asynchronously — a write may return before all cores can see it, so stale values (in real time) can be observed.
- The order in which writes become visible must obey the consistency model.
- Pipeline and coherence protocol jointly enforce the model’s orderings.
- Emerged for throughput-oriented GP-GPUs; rose to prominence after the first edition. Covered in Chapter 10.
A worry the book preempts in a footnote: does lazy propagation doom us to weak consistency? No — it is possible to enforce a variety of consistency models this way, including strong ones like SC and TSO. The category changes who does the enforcement work, not which models are reachable.
From here through Chapter 9, “coherence” means the consistency-agnostic kind, whose atomic-memory illusion the next section pins down as two invariants.
Check yourself
1.What are the two methods of the coherence interface?
2.In consistency-AGNOSTIC coherence, what does the coherence box look like to the rest of the system?
3.In consistency-DIRECTED coherence, a write may return before all cores can see it. What must the protocol still guarantee?
4.Who enforces the consistency model's orderings in each category?