Shared memory beyond the CPU
Modern computer systems are predominantly heterogeneous. The processor in a mobile phone is not just a multicore CPU: it packs a GPU and other accelerators — neural-network hardware, for instance — onto the same chip. And in the quest for programmability, these heterogeneous systems are starting to expose a single shared memory shared memory system A system in which processor cores read and write a single shared address space. defined in Chapter 1 — open in glossary across all of those compute units, which drags every question from this chapter — what ordering is guaranteed? can a cached copy go stale? — across the CPU boundary.
A heterogeneous SoC: CPU cores, GPU, and accelerators all reading and writing the same shared address space.
GPUs: life without hardware coherence
GPUs are arguably today’s most popular accelerators, and they made a choice that will look bold after chapters 6–9: they originally did not support hardware cache coherence cache coherence Making caches functionally invisible by propagating one processor's writes to other processors' caches; a means of supporting a consistency model, not a correctness definition itself. defined in Chapter 1 — open in glossary at all. The choice was rational. GPUs were designed for embarrassingly parallel graphics workloads whose threads hardly synchronize or share data — if copies almost never conflict, the hardware to keep them in sync buys little.
The bill arrives when GPUs are put to work on general-purpose workloads (GPGPU) with fine-grained synchronization and data sharing. Without hardware coherence, such programs face programmability challenges (the programmer must reason about stale copies) and/or performance challenges (crude workarounds like flushing whole caches at synchronization points).
Chapter 10 examines the promising coherence alternatives that overcome these limitations. Their common theme connects back to the two protocol classes of §1.2: rather than implementing coherence in a consistency-agnostic manner (writes propagate synchronously, caches always invisible), the candidate GPU protocols enforce the consistency model directly — they propagate values lazily, exactly when the memory model requires them to be visible. The chapter closes with a brief discussion of consistency and coherence across CPUs and accelerators, where different compute units may even live under different memory models.
Check yourself
1.Why did early GPUs choose NOT to support hardware cache coherence?
2.What goes wrong when a coherence-less GPU is used for general-purpose computing?
3.How do the promising GPU coherence protocols of Chapter 10 differ from the CPU-style protocols of Chapters 6–9?