4.1Motivation for TSO/x86

The most important model after SC

Total store order (TSO) is a widely implemented memory model: first introduced by SPARC, and — more importantly — it appears to match the memory model of x86. RISC-V supports a TSO extension (RVTSO), partly to ease porting of x86/SPARC code. This chapter follows the same pattern as chapter 3: motivation here, intuition (§4.2), formalism (§4.3), implementation including atomics and FENCEs (§4.4), further reading (§4.5), and a head-to-head comparison with SC (§4.6).

Write buffers: too valuable to lose

Cores have long used write (store) buffers write buffer Per-core FIFO holding committed stores until the cache can accept them; hides store-miss latency. defined in Chapter 4 — open in glossary to hold committed stores until the rest of the memory system can process them. A store enters the buffer when it commits and exits when the block is in the cache in a read-write coherence state — meaning a store can enter before the cache has write permission. The buffer thus hides store-miss latency, and since stores are common, avoiding those stalls matters. It also just seems sensible: the core isn’t waiting for anything — a store updates memory, not core state.

On a single-core processor, the buffer can be made architecturally invisible: ensure a load to A returns the most recent (program-order) store to A — either by bypassing bypassing A load returning the value of its own core's latest program-order-earlier buffered store, overriding memory order. defined in Chapter 4 — open in glossary the buffered value to the load or by stalling the load until the store leaves the buffer.

When building a multicore, it seems natural to give each core its own bypassing write buffer and assume the buffers remain invisible.

That assumption is wrong

Take the Dekker program once more, on a multicore with in-order cores and single-entry write buffers, and watch the buffers betray you:

The net result is (r1, r2) = (0, 0) — an execution result forbidden by SC (§3.4 showed the constraint cycle). Without write buffers this hardware is SC; with them it is not. On a multicore, write buffers are architecturally visible.

Confirm it with the litmus explorer — under pure SC three outcomes are possible; enabling Store→Load reordering (which is precisely what a write buffer does) reveals the fourth:

Three ways out

1. Turn the buffers off. Vendors have been loath to do this — the performance cost is real.
2. Hide them again with aggressive, speculative SC implementations (§3.8-style). Possible, but it adds complexity and can waste power detecting violations and handling mis-speculations.
3. Change the model. SPARC, and later x86, abandoned SC for a model that allows straightforward use of a FIFO write buffer per core: TSO total store order (tso) SC minus the Store→Load ordering rule: legalizes per-core FIFO write buffers; the SPARC/x86 memory model. defined in Chapter 4 — open in glossary , which simply allows (r1, r2) = (0, 0).

The third choice astonishes some people. But TSO turns out to behave like SC for most programming idioms — and it is well defined in all cases. The next section shows exactly what changed.