Glossary

Every term the book defines — 58 of them — with the chapter that introduced it. These are the same definitions behind the dotted-underline tooltips throughout the site.

58 shown

accuracy ch. 3: Quality of the result for a given task; units depend on the task (% correct for classification, mAP for detection) and must be read against task/dataset difficulty.
adc ch. 10: Analog-to-digital converter — in PIM it resolves the accumulated bit-line value. Its bit count, area (pitch-matching), power, and thermal noise are the central peripheral bottleneck.
angle sensitive pixels ch. 10: An image-sensor design whose pixels respond to spatial gradients — computing first-layer-like feature maps in-sensor, cutting readout ~10× and potentially replacing the DNN's first layer.
array utilization ch. 10: The fraction of a PIM array's storage elements doing useful work; drops when the workload's dimensions (C·H·W, M) under-fill the array's rows (B) and columns (A).
batching ch. 3: Processing multiple inputs together to amortize overhead such as loading weights; raises throughput but also raises latency.
bit line ch. 10: The column wire of a memory array; in processing-in-memory it accumulates per-cell products (current or charge) into a partial sum read by the ADC (BL).
bit-serial processing ch. 10: Building multi-bit arithmetic from 1-bit operations across multiple cycles — how DRAM PIM composes AND/OR into MACs, and how 1-bit storage elements handle multi-bit weights (with shift-and-add).
charge-based pim ch. 10: PIM style that multiplies/accumulates via charge sharing on capacitors (8T SRAM XNOR cells, DRAM); more linear, limited by capacitance ratios.
coherent detection ch. 10: Optical scheme encoding weights and activations on-the-fly into light interfered on a beamsplitter — an output-stationary optical dataflow without on-chip interferometers.
cross-point element ch. 10: A resistive storage device placed directly at the crossing of two wires, in some cases without an access transistor — maximizing memristor array density.
current-based pim ch. 10: PIM style that multiplies via device I-V characteristics and accumulates by current summing on the bit line (NVM, 6T SRAM); sensitive to nonlinearity and variations.
dac ch. 10: Digital-to-analog converter — in PIM it drives inputs onto word lines; its cost scales with input precision, hence 1-bit DACs plus time coding in practice.
data reuse ch. 3: Moving a datum once from large distant memory and using it for many operations out of small local memory, cutting data-movement energy and bandwidth.
dataflow ch. 3: The order of operations and where data is stored and reused in a DNN accelerator; determines how often each piece of data moves.
differential signaling ch. 10: Representing a signed weight with two storage elements (often two arrays) — needed because resistance/conductance cannot be negative.
edram ch. 10: Embedded DRAM fabricated on the compute die — tens of MB on-chip; denser than SRAM but costlier to fabricate and scaling more slowly.
effectual operation ch. 3: A MAC whose inputs are both non-zero, so it changes the accumulated value. Ineffectual MACs (a zero operand) do not, and can in principle be skipped.
energy efficiency ch. 3: Task executions per unit energy; for DNN inference, inferences per joule (or its inverse, joules per inference).
eyexam ch. 3: A systematic framework (extending the roofline model) for understanding DNN processor performance limits; detailed in the full book's Chapter 6, not in this excerpt.
flexibility ch. 3: The range of DNN models a processor supports — functionally (tier 1) and while maintaining efficiency (tier 2).
hardware cost ch. 3: Monetary cost to build a system; proxied by chip area (with process node) and off-chip bandwidth (packaging/PCB).
hbm ch. 10: High Bandwidth Memory — commercialized 3-D stacked DRAM standard reached over very wide in-package interfaces; also a packaging cost driver in §3.4.
hmc ch. 10: Hybrid Memory Cube — commercialized 3-D stacked DRAM connected by TSVs, organized into vaults (vertically stacked banks); the basis of Neurocube and Tetris.
latency ch. 3: Time between input data arriving at the system and the result being generated; reported in seconds.
little's law ch. 3: Queuing-theory relation: throughput = tasks-in-flight / latency. Explains why batching's extra inferences-in-flight trade latency for throughput.
mac operation ch. 3: Multiply-accumulate, the dominant operation in DNN processing; the book uses 'operations' and 'MAC operations' interchangeably.
mapping ch. 3: The placement and scheduling, in space and time, of every MAC operation and its operand delivery onto the PEs — a compiler for DNN hardware.
mean average precision ch. 3: Accuracy metric for object detection (mAP), capturing the trade-off between true- and false-positive rates.
memory wall ch. 10: The energy and bandwidth bottleneck of moving data between off-chip memory (e.g., DRAM) and the processor.
memristor ch. 10: A programmable resistive NVM element: conductance G encodes a weight, so Ohm's law I = V·G multiplies and Kirchhoff current summing accumulates.
mlperf ch. 3: Industry/academic benchmark suite of well-studied DNN models for fair comparison of DNN hardware and frameworks, for training and inference.
monolithic 3-d integration ch. 10: Fabricating thin layers of logic and memory directly on top of each other, connected by interlayer vias (ILVs) that are orders of magnitude denser than TSVs.
off-chip bandwidth ch. 3: Data rate between the chip and external memory or other chips (Gbps); a proxy for packaging and PCB cost.
operational intensity ch. 3: Compute per byte of data moved (ops/byte); decides whether a workload is bandwidth-limited or compute-limited.
optical neural network ch. 10: DNN processing with photons: passive multiplication via interferometer meshes or free-space coherent detection; energy goes to electro-optical conversion, and optical non-idealities cost accuracy.
peak performance ch. 3: Theoretical maximum throughput: every PE computing every cycle (100% utilization).
pitch-matching ch. 10: Fitting a peripheral circuit (typically the ADC) into the physical width of an array column; when impossible, the ADC is time-multiplexed across columns, cutting parallelism.
power consumption ch. 3: Energy consumed per unit time (watts); together with energy efficiency it bounds achievable throughput.
processing element ch. 3: A simple or primitive core that performs a single MAC operation; the unit of parallelism in a DNN accelerator (PE).
processing in memory ch. 10: Performing MACs inside the weight memory itself: inputs drive word lines, storage elements multiply, bit lines accumulate; only results are read out (PIM / in-memory computing).
processing in sensor ch. 10: Moving early DNN computation before or inside the image sensor's ADC (switched-capacitor MACs, Angle Sensitive Pixels) to cut input-data movement.
processing near memory ch. 10: Bringing digital compute physically close to high-density memory (eDRAM, 3-D stacks) to shorten interconnect: lower access energy, wider and faster interfaces. Also called near-data processing.
pulse-width modulation ch. 10: Encoding an input activation in time at fixed voltage (unary pulses) so a 1-bit DAC suffices; robust to nonlinearity, but costs cycles.
read disturb ch. 10: Accidentally flipping an SRAM bit cell while reading; limits allowable bit-line swing in SRAM PIM or costs extra isolation transistors.
ron / roff ch. 10: A resistive NVM device's low/high resistance states (also LRS/HRS). Their separation, against bit-line resistance, bounds how reliably stored weights can be sensed (Eq. 10.2).
roofline model ch. 3: Plot of achievable ops/sec vs operational intensity: a bandwidth-limited slope up to an inflection point at the compute-limited peak.
scalability ch. 3: How well a design scales throughput and efficiency when resources (PEs, storage, chiplets) are replicated without redesign.
sense amplifier ch. 10: A bit-line circuit that amplifies a small voltage difference to full swing; in DRAM PIM it resolves the majority function after triple-row charge sharing.
sparsity ch. 3: The fraction of zeros in weights/activations; exploiting it means skipping ineffectual MAC operations.
stacked memory ch. 10: Memory dies stacked on the logic die, connected by TSVs (HMC, HBM) or inductive-coupling TCI — roughly 10× bandwidth and up to 5× lower access energy than 2-D DRAM. Also called 3-D or in-package memory.
switching activity ch. 3: α in energy/operation = α·C·V²DD: how often the switched capacitance is actually charged.
thermal design power ch. 3: The power a system's cooling is designed to dissipate (TDP); the ceiling on sustained power consumption.
through-silicon via ch. 10: A vertical electrical connection through a die that enables 3-D stacking, with much lower capacitance than off-chip traces (TSV).
throughput ch. 3: Amount of data processed or task executions completed per unit time; for DNN inference, inferences per second.
thruchip interface ch. 10: TCI — inductive-coupling die-to-die wireless communication for stacked dies (used by Quest's stacked SRAM); lower integration cost than TSVs.
unexploited ineffectual operation ch. 3: An ineffectual MAC the hardware fails to skip, so it still costs a cycle and energy.
utilization of pes ch. 3: Fraction of peak throughput actually achieved: (number of active PEs / number of PEs) × utilization of those active PEs.
word line ch. 10: The row wire of a memory array; in processing-in-memory it delivers the input activation (voltage or pulse train) to every storage element in the row (WL).