Part I limited the array’s size and its rows. This page finishes the challenge catalog — columns, input delivery, and the multi-bit MAC itself — then totals what is left of the “one-cycle” dream on the toy example ([1, 2, 0, 3] × the 4×4 filter → [7, 13, 10, 5]).
Challenge 4 — columns activated in parallel (Fig. 10.13)
Ideal: all A columns at once. Reality: each column’s dot product must pass through an ADC adc Analog-to-digital converter — in PIM it resolves the accumulated bit-line value. Its bit count, area (pitch-matching), power, and thermal noise are the central peripheral bottleneck. defined in ch. 10 — open in glossary , and for a compact layout the ADC’s area must pitch-match the width of the column — nearly impossible next to high-density storage elements like NVM devices. The common fix: time-multiplex one ADC across a set of eight columns, so only A/8 columns are live per cycle. On the toy array, with an ADC spanning two columns:
Two cycles: columns 0–1 resolve their full dot products first, then columns 2–3. Design 24’s loop nest: the column loop splits into parallel-for m1 in [0, M/2) with a temporal for m0 in [0, 2). Unlike the row limit, each column still finishes in one shot — no cross-cycle accumulation needed — but throughput still halves.
And the limits compose. Rows capped at 2 and columns capped at 2:
Each column group must sit through every row group: ceil(4/2) × ceil(4/2) = 4 cycles. The average parallelism is down to 4 MACs/cycle from the theoretical 16.
Challenge 5 — time to deliver the input (Fig. 10.14)
Ideal: all input bits encoded onto the word line at once — voltage amplitude modulation. Reality, per the book, two obstacles:
- device nonlinearity makes amplitude encoding unreliable (recall the bowed transfer curve of 10.2.2);
- DAC complexity scales with the number of input bits.
So inputs are usually encoded in time at a fixed voltage — pulse-width modulation pulse-width modulation Encoding an input activation in time at fixed voltage (unary pulses) so a 1-bit DAC suffices; robust to nonlinearity, but costs cycles. defined in ch. 10 — open in glossary or pulse-count (unary) coding with a 1-bit DAC — and the partial sum accumulates as charge over the pulses. (Footnote 17: discrete pulses are even more robust to nonlinearity than one long pulse, at the cost of switching activity — an α increase in Eq. 3.8’s energy. Footnote 18: the dual trade exists too — keep a single pulse but replicate the weights across 2^N−1 rows for an N-bit input: time exchanged for area.) Reducing input precision (the full book’s Chapter 7) shortens the pulse trains but costs accuracy. Step through the toy example — input [1, 2, 0, 3] becomes three unary slices:
1t = 0 — first pulse slice [1, 1, 0, 1]
Every input ≥ 1 fires a pulse. The array computes a binary-input matrix-vector product: [1,1,0,1] × weights = [3, 6, 6, 3], which starts accumulating as charge.
Challenge 6 — time to compute a MAC (Fig. 10.15)
Ideal: one cycle per MAC. Reality: the storage element typically performs only 1-bit operations (XNOR, AND — as in the 8T SRAM cell or 1-bit-per-memristor NVM), so multi-bit arithmetic is built up bit-serially: the toy’s 2-bit weights spread across 8 columns (MSB and LSB per weight, the Fig. 10.8 layout), each column accumulates its per-bit totals across the input slices, and post-ADC shift-and-add logic combines each MSB/LSB pair (MSB total × 2 + LSB total) into the true psum:
1Input slices run against 1-bit weight columns
Three PWM slices (as in Fig. 10.14) drive the 8 one-bit columns. After t = 0 ([1,1,0,1]), the per-column accumulations are [1,1,2,2,2,2,1,1] — separate MSB and LSB tallies per weight, not yet real psums.
The total bill
| term | meaning | units | dictated by |
|---|---|---|---|
| rows in array vs rows activated per cycle (ADC bits, variation, BL current) | rows | challenge 3 | |
| columns in array vs columns per cycle (ADC pitch-matching / multiplexing) | cols | challenge 4 | |
| input time slices (PWM pulses ≈ max input value; 1 if amplitude-encoded) | cycles | challenge 5 |
The toy example at its book settings: ⌈4/2⌉ × ⌈4/2⌉ × 3 = 12 cycles — 1.3 effective MACs/cycle from a 16-MAC array. Now try a “realistic” NVM config: B = A = 256, B_par = 64, A_par = 32 (256/8), T_in = 15 for 4-bit PWM inputs → 480 cycles and ~136 MACs/cycle from a 65,536-MAC array. The crossbar’s headline parallelism and its delivered parallelism differ by orders of magnitude — and bit-serial weight handling (challenge 6) still adds its shift-add cycles on top.
What 10.2.4 really says
Each challenge is the same story in a different domain: the array computes for free, but getting signals in and out truthfully (enough ADC bits, matching pitch, linear input encoding, multi-bit weights) is where the physics pushes back — and every countermeasure spends cycles, area, energy, or accuracy. When you read a PIM paper’s TOPS/W headline, 10.2.4 is the checklist of what to look for in the fine print — alongside §3.7’s reporting rules.
Check yourself
Check yourself — PIM Design Challenges II
1.Why can't every column have its own ADC?
2.Why do practical PIM designs deliver inputs as pulse trains (1-bit DAC) instead of voltage amplitudes?
3.Under PWM input delivery, the toy input [1,2,0,3] is signaled as [1,1,0,1] + [0,1,0,1] + [0,0,0,1]. Predict the accumulated psums after the second cycle.
4.A storage element can only do 1-bit operations (XNOR/AND). What completes a multi-bit MAC, and what does it cost?
5.Tally the toy example's bill: rows limited to 2 of 4, ADC spanning 2 of 4 columns, and 3 PWM input slices. How many cycles for the 'one-cycle' array?