The previous page used exotic devices — memristors, floating gates. This page shows the same in-memory computing idea built from the two mainstream memory cells: SRAM (10.2.2) and DRAM (10.2.3). The physics changes (currents → charge), and with it the failure modes and the shape of the parallelism.
10.2.2 SRAM bit cells that multiply
SRAM-PIM designs split into the same two families introduced for NVM:
Current-based: ride the pull-down network
Encode the input activation as a voltage amplitude on the word line. That voltage controls the current through the bit cell’s pull-down network (IBC), producing a bit-line voltage drop ΔVBL proportional to the word-line voltage. Weights are ±1: storing a 0 (weight −1) steers the drop onto BL, storing a 1 (weight +1) onto BLB — and the currents of all cells on a column add (the current-based current-based pim PIM style that multiplies via device I-V characteristics and accumulates by current summing on the bit line (NVM, 6T SRAM); sensitive to nonlinearity and variations. defined in ch. 10 — open in glossary accumulation again).
Figure 10.5(a), distilled. Left: word-line voltage × stored ±1 weight becomes a current that drops BL or BLB; a column’s currents sum. Right: the voltage-to-current transfer curve is nonlinear and varies device to device — the current-based family’s precision ceiling.
Charge-based: compute with capacitor ratios
The transfer-curve problem motivates the charge-based charge-based pim PIM style that multiplies/accumulates via charge sharing on capacitors (8T SRAM XNOR cells, DRAM); more linear, limited by capacitance ratios. defined in ch. 10 — open in glossary family: perform the multiplication by charge sharing, where results depend on capacitance ratios — much more linear and less variation-sensitive. Figure 10.5(b)‘s 8T multiplying bit cell does a digital binary multiplication — an XNOR between the stored weight and the input activation (an AND mode also exists: hold IA high) — and conditionally charges a local capacitor; the analog accumulation then happens by charge sharing across the local capacitors of all cells on the column, producing the pre-activation value. Variants multiply directly with the bit line, or charge-share across different bit lines to accumulate.
Figure 10.5(b), distilled: the 8T multiplying bit cell separates concerns — digital multiplication, analog (charge-ratio) accumulation.
The stability tax
SRAM-PIM’s characteristic hazard: read disturb read disturb Accidentally flipping an SRAM bit cell while reading; limits allowable bit-line swing in SRAM PIM or costs extra isolation transistors. defined in ch. 10 — open in glossary . The bit-line swing must stay small or reading can flip the cross-coupled storage node — an accidental write. But PIM wants many accumulated levels on that same bit line (conventional SRAM resolves exactly one bit there). The two escapes both cost: keep the swing low (fewer psum bits), or add isolation transistors (the 8T route — bigger cell, lower area density).
Reality check — and what SRAM-PIM is actually for
SRAM-PIM results come from fabricated test chips — ahead of NVM there — but demonstrate MNIST-scale models with layer-by-layer weight updates, and often with DNN layer shapes custom-designed to fit the array for utilization: the §3.5 flexibility concern again. And the book’s footnote 10 keeps the scope honest: SRAM is less dense than DRAM, so these designs don’t attack the off-chip memory wall memory wall The energy and bandwidth bottleneck of moving data between off-chip memory (e.g., DRAM) and the processor. defined in ch. 10 — open in glossary — they reduce on-chip data movement.
10.2.3 DRAM: logic by majority vote
DRAM-PIM computes with the humblest element of all: the bit-cell capacitor. Activate three rows at once and the bit line settles on the average of the three capacitors’ charge. If cells X, Y, Z store logical values, the sense amplifier sense amplifier A bit-line circuit that amplifies a small voltage difference to full swing; in DRAM PIM it resolves the majority function after triple-row charge sharing. defined in ch. 10 — open in glossary resolves the majority function XY + YZ + ZX — and the third input is the opcode: Z = 1 makes it OR(X, Y); Z = 0 makes it AND(X, Y). Step through Figure 10.6:
1t = 0 — precharge (case: Z=0, AND(X=1, Y=1))
Each bit cell’s capacitor holds V_DD for a stored one, 0 for a zero. The bit line is precharged to the midpoint V_DD/2. Access transistors are still off. Note this computation will DESTROY the stored values — real designs copy the operands first.
Why DRAM-PIM’s parallelism looks different
The book contrasts the architecture against NVM/SRAM-PIM on two axes:
- Operands per op: a DRAM bit-wise op consumes three storage elements from different rows; NVM/SRAM do a MAC in one element.
- Where accumulation happens: DRAM performs one op per bit line, accumulating over time; NVM/SRAM accumulate many MACs on the bit line at once.
So DRAM parallelism exists only across bit lines (A) — not across rows (B) too — and each MAC takes multiple cycles to assemble from bit-wise ops. The design challenge: enough bit-line parallelism (A) to still win on throughput. Further practical hurdles: capacitance variation between cells, charge leaking over time, sensing tiny bit-line excursions, and the extra memory-controller hardware to activate multiple rows and orchestrate the bit-serial MAC assembly — all energy/area overhead.
The off-the-shelf demonstration
While most DRAM-PIM results are simulated, AND/OR operation has been demonstrated on unmodified commercial DRAM — by violating the nominal timing specification: activating multiple rows in rapid succession leaves them open simultaneously, and the bit line’s charge sharing does the rest. The compute primitive is latent in the commodity part.
The three technologies, side by side
| NVM (10.2.1) | SRAM (10.2.2) | DRAM (10.2.3) | |
|---|---|---|---|
| Multiplication | device physics: I = V·G (or floating-gate I-V) | current: pull-down I-V · charge: digital XNOR | bit-wise AND/OR via 3-row majority |
| Accumulation | current summing on BL (Kirchhoff) | current summing or cap charge sharing | over time, across cycles |
| Parallelism | A × B (rows and columns) | A × B (rows and columns) | A only (across bit lines) |
| Characteristic hazard | write cost · variation · no negative G | read disturb ↔ swing ↔ area | leakage · cap variation · destructive ops |
| Demonstrated (at book time) | sim: VGG/ImageNet · fab: MNIST, ≤32 rows, 1b cells | fabricated chips — MNIST, layer-by-layer | mostly sim; AND/OR shown on commodity DRAM |
Design takeaway
Across all three technologies the pattern repeats: the multiply is almost free, and the entire engineering fight is over the read-out path — swing, disturb, noise, converters. That fight is priced item by item in the next two pages, Design Challenges I and II.
Check yourself
Check yourself — SRAM & DRAM PIM
1.Why do charge-based SRAM designs exist at all, given current-based ones came first?
2.What is 'read disturb', and what does it cost SRAM-PIM designs?
3.In DRAM triple-row activation, three cells X, Y, Z charge-share onto the bit line. What logic function does the sense amplifier resolve, and how does Z select the operation?
4.Predict the parallelism consequence of DRAM-PIM's architecture versus NVM/SRAM-PIM.
5.What did the 'unmodified commercial DRAM' demonstration show, and how?