Interactive edition · excerpt

Efficient Processing of Deep Neural Networks

An interactive study companion to the book by Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, and Joel S. Emer (MIT) — Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2020. Every section is rebuilt as labeled diagrams, annotated equations, step-through animations, and quizzes — the same ideas, made visual.

11 interactive sections 58 glossary terms 7 widget types Glossary →
Your reading progress 0 / 11

About this excerpt: the source PDF contains only the chapters that are complete in it — Chapter 3 (Key Metrics and Design Objectives), Chapter 10 (Advanced Technologies), and Chapter 11 (Conclusion). Chapters 1–2 and 4–9 of the full book (DNN background, kernel computation, dataflows, mapping, precision, sparsity, and NAS) are not included; where the text refers to them, the pages explain the needed idea inline — and the Conclusion page's coverage map shows exactly where each missing chapter would slot in.

The learning path

Read top to bottom — Chapter 3's metrics are the yardstick Chapter 10 applies, and Chapter 11 ties both into the book's design method. Use ← / → to move between sections; ✓ marks what you've read.

Part II — Design of Hardware for Processing DNNs

How to judge a DNN accelerator before building one — accuracy, throughput and latency, energy and power, hardware cost, flexibility, and scalability, and why the metrics must be reported together.

3 Key Metrics and Design Objectives pp. 50–63 0/4
  1. 3.1 Accuracy
  2. 3.2 Throughput and Latency
  3. 3.3 Energy Efficiency and Power Consumption
  4. 3.4-3.7 Hardware Cost, Flexibility, Scalability & Interplay
the metric vector defined here is how every technology below gets judged

Part III — Co-Design of DNN Hardware and Algorithms

Moving compute to the data instead of data to the compute — processing near memory (3-D stacked DRAM, eDRAM), processing in memory (NVM, SRAM and DRAM bit cells that multiply), in-sensor and optical computing, and the analog-circuit realities that make these designs hard.

10 Advanced Technologies pp. 242–267 0/6
  1. 10.1 Processing Near Memory
  2. 10.2.1 Processing in Memory: Fundamentals & NVM
  3. 10.2.2-10.2.3 Processing in Memory: SRAM & DRAM
  4. 10.2.4a PIM Design Challenges I — Storage & Array Geometry
  5. 10.2.4b PIM Design Challenges II — Parallelism, Time & Circuit Non-Idealities
  6. 10.3-10.4 Processing in Sensor & in the Optical Domain
technologies + metrics feed the closing design method

Conclusion

The whole design space in one view — how metrics, dataflows, co-design, and advanced technologies fit together, and where the full book’s missing chapters would slot in.

11 Conclusion pp. 268–269 0/1
  1. 11 Conclusion
Content faithful to Efficient Processing of Deep Neural Networks by V. Sze, Y.-H. Chen, T.-J. Yang, and J. S. Emer (Synthesis Lectures on Computer Architecture, Morgan & Claypool, 2020), rewritten as an original web-native, interactive edition for personal study.