Now that we know how raw flash behaves, we can build an actual SSD out of it.
44.4 Performance and Reliability
The raw operations have very different costs, and packing more bits per cell slows them further:
| read a page (Β΅s) | program a page (Β΅s) | erase a block (Β΅s) | |
|---|---|---|---|
| SLC | 25 | 200β300 | 1500β2000 |
| MLC | 50 | 600β900 | ~3000 |
| TLC | ~75 | ~900β1350 | ~4500 |
The main reliability worry is wear out wear out Flash's main reliability limit: each program/erase (P/E) cycle leaves a little extra charge in a block until 0s and 1s can no longer be told apart and the block dies. Rated lifetimes are ~10,000 P/E cycles (MLC) to ~100,000 (SLC). Avoiding uneven wear is why SSDs do wear leveling. defined in ch. 44 β open in glossary : every program/erase (P/E) cycle leaves a little extra charge in a block, until 0 and 1 can no longer be told apart and the block dies (rated ~10,000 P/E cycles for MLC, ~100,000 for SLC). Thereβs also disturbance β reading or programming a page can flip bits in neighbors.
44.5 From Raw Flash to an SSD: The FTL
An SSD wraps flash chips (plus some volatile SRAM and control logic) behind the standard block interface. The brains is the flash translation layer (FTL) flash translation layer The FTL: the SSD's control logic that presents a normal logical block interface while translating client reads/writes into low-level flash read/erase/program operations. It aims for high performance (low write amplification, chip parallelism) and reliability (wear leveling), typically via a log-structured design + a mapping table. defined in ch. 44 β open in glossary , which turns client reads/writes on logical blocks into low-level read/erase/program on physical pages:
Two FTL goals drive everything: keep performance high (use many chips in parallel and minimize write amplification write amplification The ratio of write traffic the FTL actually issues to the flash divided by the write traffic the client issued to the SSD. Extra writes come from garbage collection, block-mapping copies, and wear leveling. High write amplification wastes flash endurance and hurts performance; minimizing it is a core FTL goal. defined in ch. 44 β open in glossary β the flash write traffic issued divided by the client write traffic), and keep reliability high via wear leveling wear leveling The FTL activity that spreads program/erase cycles evenly across all blocks so they wear out at roughly the same time (rather than a few hot blocks dying early). Log-structuring helps, but the FTL must also periodically migrate long-lived data out of cold blocks so those blocks take their share of writes. defined in ch. 44 β open in glossary (spread erases evenly so all blocks wear out together, not a few hot ones early).
44.6 A Bad FTL: Direct-Mapped
The simplest FTL β direct-mapped direct-mapped ftl The naive FTL where logical page N maps straight to physical page N. Every write must read the whole containing block, erase it, and re-program all pages β causing huge write amplification, terrible write speed, and rapid wear of hot blocks. A bad idea, motivating the log-structured FTL. defined in ch. 44 β open in glossary β maps logical page N straight to physical page N. Reads are fine, but every write must read the whole containing block, erase it, then re-program all its pages plus the new one. Thatβs enormous write amplification (proportional to pages per block), write performance worse than a disk, and β because a repeatedly-overwritten logical block hammers the same physical block β rapid wear out. A bad idea on both counts.
44.7 A Log-Structured FTL
So most FTLs are log-structured log-structured ftl The dominant FTL design: on a write to logical block N, append the data to the next free page (logging) and record N β physical-page in a mapping table. This turns random writes into sequential ones (few erases), improves performance, and spreads wear β the same log idea as LFS, inside the device. Its costs: garbage collection and mapping-table size. defined in ch. 44 β open in glossary β the very idea from LFS, now inside the device. On a write to logical block N, the FTL just appends the data to the next free page and records N β physical-page in a mapping table:
1Empty device, empty map
All pages are INVALID and the mapping table is empty. The client will write logical blocks 100, 101, 2000, and 2001.
This is a huge win: random client writes become sequential programs (erasing only occasionally), the costly read-modify-write is gone, and wear is spread across pages. The mapping table (kept in SRAM, and persisted β e.g. in each pageβs out-of-band area β so it survives power loss) is the FTLβs version of LFSβs inode map. But log-structuring brings the same two costs LFS had: garbage from overwrites, and a potentially huge mapping table β the subjects of the next page.
Check yourself: flash reliability and the FTL
1.How do the raw flash operation costs compare?
2.What is flash 'wear out'?
3.What does the flash translation layer (FTL) do?
4.What is write amplification, and why minimize it?
5.Why is a direct-mapped FTL (logical page N β physical page N) a bad idea?
6.How does a log-structured FTL work, and why is it better?