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Contents

A machine that only understands 32-bit numbers

Section 1.1 8 min read

  • instruction
  • instruction set architecture (ISA)
  • RISC
  • word
  • hexadecimal

Checked against: MIPS32 Vol. I §1–2 (the architecture) carolyne_ref/smoke_program.py carolyne_ref/dumps/hello_o0.dump

Before you start

  • Nothing. If you know RISC-V, every section will tell you what transfers and what does not.

By the end, you can

  • Say what a CPU actually receives: a list of 32-bit words, one instruction each
  • Explain what an ISA is, and why two very different cores can run the same words
  • Read one 32-bit word as bits, as eight hex digits, and as a decimal number
  • State the two RISC rules MIPS follows

A program is a list of numbers

Open a compiled MIPS program in memory and you see only numbers. Here are the first four words of a real program. This program ran on your own core.

addressthe word (hex)what it means
0xBFC000000x3C081000put 0x1000 in the top half of register $t0
0xBFC000040x35080FF0OR 0x0FF0 into the bottom half of $t0
0xBFC000080x24090048put the number 72 (the letter H) in $t1
0xBFC0000C0xAD090000write $t1 to the memory address held in $t0

Each row is one . The CPU works in a simple loop:

  1. Read the word at the address in the (the PC).
  2. Do what the bits say.
  3. Add 4 to the PC, because every instruction is 4 bytes long.

That is the whole machine, seen from the outside. In §1.2 you will watch it run this exact program, one instruction at a time.

The contract: who writes the numbers, who obeys them

Nobody writes those hex words by hand. A chain of tools writes them, and a chip obeys them. The agreement between the two sides has a name: the , or ISA.

Where the instruction set sits: the line between the words and the machine

Everything above the line writes 32-bit words. Everything below the line obeys them.

SOFTWARE — writes the words hello.c for (i = 0; i < 5; i++) assembly text addiu $v0,$v0,1 32-bit words 0x24420001 gcc as + ld memory at 0xBFC00000 the reset vector the ISA: the contract "these 63 instructions, 32 registers, byte-addressed memory, a delay slot after every branch" HARDWARE — obeys the words, any way it likes MIPS R2000 (1985) 5-stage pipeline, one instruction per cycle, in order — the design the delay slot was made for runs the same words Carolyne's core (2026) out-of-order, register renaming, two lanes — the same engine also runs RISC-V runs the same words

What to notice

The dashed line is the ISA. Above it, three tools turn C into words. Below it, two cores built forty years apart run the same words. The words never change to fit the core. That is the point of a contract.

You already know this from your own project. Carolyne’s engine runs both MIPS and RISC-V. The engine did not change between them. Only the description of the contract changed. So the ISA is not the chip. It is the promise the chip keeps.

Before reading on, decide:

A colleague says: 'Carolyne runs MIPS, so it must contain a MIPS pipeline.' Is that right?

What MIPS is, in six lines

  • 1985. Designed at Stanford University by a team led by John Hennessy.
  • The name. “Microprocessor without Interlocked Pipeline Stages”. The last three words are a design choice you will meet in §5.4.
  • The classic teaching ISA. For thirty years, most architecture courses used MIPS. It is small and regular.
  • Real products. Routers, game consoles (Nintendo 64, PlayStation 1 and 2), printers, set-top boxes.
  • Release 2 (2002). Added a handful of useful instructions. Chapter 8 is about them. Your compiler flag -march=mips32r2 names this release.
  • Today. MIPS the company moved to RISC-V. The ISA lives on in courses, in old hardware, and in your own core.

Why learn MIPS in 2026? RISC-V was designed by people who taught MIPS. MIPS is the cleanest example of the ideas RISC-V refined. And your engine runs it. The same 17 programs that run on your RV32IM core run on your MIPS core. They matched their host builds on the first try.

What “RISC” means

MIPS is a design. For this book, RISC means two rules:

  1. Every instruction is one 32-bit word. The fetch unit always knows where the next instruction starts: 4 bytes further on.
  2. Only loads and stores touch memory. An add never reads memory. You load a value into a register, add, and store the result back.

One word, three ways

Every word in this book is written in . A hex digit is exactly four bits. So a 32-bit is exactly eight hex digits. That is why 0x24090048 has eight digits after the 0x.

Below is that word, drawn three ways. Hover a hex digit. The four bits that digit stands for light up. Click a bit to flip it and watch the digit change.

One word, three ways: bits, hex, decimal

Which four bits does each hex digit stand for?

bit 31bit 27bit 23bit 19bit 15bit 11bit 7bit 3
the 32 bits
hex0x24090048← hover a digit to see its four bits

decimal, read as a plain count: 604569672

  • the four bits of the hovered hex digit

Click any input bit to flip it.

What to notice

Bit 31 is on the left, bit 0 on the right, always. The first hex digit (2) is bits 31 to 28. The last digit (8) is bits 3 to 0. The decimal value is the same number written a third way — it is not a different value. A word whose bit 31 is set can also be read as a negative number. That is two’s complement, explained in §3.1.

The word 0x24090048 is addiu $t1,$zero,72. In §1.3 you will see how the bits split into fields: the top six bits say “addiu”, the next two groups of five name the registers, and the bottom sixteen hold the number 72.

Go deeper: the name, the versions, and which one your toolchain builds

The full name is Microprocessor without Interlocked Pipeline Stages. The original design (1985) refused to add hardware that stops the pipeline when a value is not ready yet. Instead the ISA promised that certain instructions would not use certain results too early. The branch delay slot (§5.4) is the last surviving piece of that promise; the load delay slot was dropped in MIPS II (1990).

The ISA versions ran MIPS I to MIPS V, then split into MIPS32 and MIPS64 (1999). MIPS32 release 2 (2002) added the instructions in chapter 8 and is what -march=mips32r2 selects. Release 6 (2014) changed encodings and removed the delay slot from some branches; it is a different ISA for our purposes and this book does not cover it.

Your toolchain also passes -mabi=32: the o32 calling convention, the subject of chapter 6. And mipsel means little-endian byte order — chapter 4.

Can you now explain it?

A program is a list of 32-bit numbers. The ISA is the agreement about what each number means. A core is any machine that keeps that agreement, by whatever method it likes.

If you remember only three things

  1. The CPU reads numbers, not text. C and assembly are for people; the assembler turns each line into one 32-bit word, and only the words reach the machine.
  2. The ISA is a contract, not a chip. It fixes what the words mean. A 1985 in-order pipeline and a 2026 out-of-order engine both keep it, and both run the same words.
  3. Eight hex digits are 32 bits. Bit 31 is on the left. Every word, address and mask on this site is written the same way, so you never decode hex in your head.

Now try to explain this one yourself: your MIPS core and your RISC-V core share one engine. They ran the same seventeen C programs. Which parts of the system had to change between the two? Which parts stayed exactly the same? Say it in terms of the contract figure.

Go deeper: a model answer, once you have tried

What changed: everything that touches the contract line. Above it, the compiler (mipsel-linux-gnu-gcc instead of riscv64-unknown-elf-gcc) writes different words for the same C. At the line, the ISA description in Carolyne (carolyne/isa/mips/ instead of carolyne/isa/riscv/) tells the engine what the words mean: which fields, which registers, which operations.

What stayed the same: the C programs, and the engine below the line — the rename tables, the reorder buffer, the stations, the load/store unit. The engine reads the description at build time and shapes itself. That is the whole research claim of your project, and it is the same claim the ISA makes in general: the words say what, the machine chooses how.

Check your understanding

0/5 answered

  1. 1.What does a MIPS CPU actually receive from a program?

  2. 2.Which of these is a fact about the ISA (the contract), and not about one particular chip?

  3. 3.How many hexadecimal digits does it take to write one 32-bit MIPS word?

    Use the 'one word, three ways' figure if you need to.

  4. 4.Which statement best describes what 'RISC' means for MIPS?

  5. 5.Carolyne's out-of-order core and a 1985 MIPS R2000 are built completely differently. Why can they run the same program words?

Next: §1.2 — the same program, run in front of you one instruction at a time.

Where this comes back

8 later sections build on this one.