Interactive textbook

MIPS32 from Zero

A visual course on the MIPS instruction set, written for one reader who knows RISC-V and has never used MIPS. Grounded in the MIPS32 Architecture For Programmers and in Carolyne's executable MIPS32 description.

Every instruction in this book is shown as bits, and every example program is run: you can play it, pause it, and step one instruction at a time while the registers, the memory and the console change in front of you. Every number you see is computed by the site's own MIPS simulator from the program's text — never typed in beside it.

The English is kept plain on purpose: short sentences, every abbreviation expanded, every technical word explained twice — once in ordinary words and once precisely.

The book's first program, running — every example on this site runs like this

PC→	bfc00000	3c081000	lui $t0, 0x1000
	bfc00004	35080ff0	ori $t0, $t0, 0x0ff0
	bfc00008	24090048	addiu $t1, $zero, 'H'
	bfc0000c	ad090000	sw $t1, 0($t0)
	bfc00010	24090069	addiu $t1, $zero, 'i'
	bfc00014	ad090000	sw $t1, 0($t0)
	bfc00018	2409000a	addiu $t1, $zero, '\n'
	bfc0001c	ad090000	sw $t1, 0($t0)
	bfc00020	240a0006	addiu $t2, $zero, 6
	bfc00024	240b0007	addiu $t3, $zero, 7
	bfc00028	014b0018	mult $t2, $t3
	bfc0002c	00006012	mflo $t4
	bfc00030	ad0c0004	sw $t4, 4($t0)
	bfc00034	ad0cfff0	sw $t4, -16($t0)
	bfc00038	8d0efff0	lw $t6, -16($t0)
	bfc0003c	ad0e0004	sw $t6, 4($t0)
	bfc00040	10000002	beq $zero, $zero, skip
	bfc00044	00000000	nop
	bfc00048	ad090004	sw $t1, 4($t0)
	bfc0004c	114b0002	beq $t2, $t3, no_star
	bfc00050	00000000	nop
	bfc00054	ad0c0000	sw $t4, 0($t0)
	bfc00058	240d0000	addiu $t5, $zero, 0
	bfc0005c	ad0d0008	sw $t5, 8($t0)
	bfc00060	1000ffff	beq $zero, $zero, park
	bfc00064	00000000	nop

registers — read · written

$t00x00000000
$t10x00000000
$t20x00000000
$t30x00000000
$t40x00000000
$t50x00000000
$t60x00000000

console

▌

tick 0 of 23 · 1 tick = 1 instruction

Twenty-four instructions from §1.2: two doors, a multiply through HI/LO, a store and a load, one taken branch and one not taken — each with its delay slot. Pause it, or open §1.2 to step through it with the explanations.

Your progress

Answer a section's quiz and it will be remembered here, in this browser only.

A path through it

28 sections in nine chapters, about 250 minutes of reading plus the time you spend stepping through the programs.

1 · Start here

What a MIPS instruction is, and where the CPU keeps its numbers

Everything later depends on these two. Chapter 1 runs a real program by hand and shows every instruction as bits; Chapter 2 is the 32 registers and the names the compiler gives them.

1. Start here: what an instruction set is

28 min

2. Registers: the 32 boxes the CPU works in

17 min

Computing with bits, and reaching memory

Arithmetic, immediates, logic and compares — every bit drawn — then memory: bytes, words, little-endian order, loads, stores and the stack.

3. Arithmetic and logic

40 min

4. Memory: bytes, words and addresses

31 min

Deciding, jumping, calling — and the delay slot

Branches and jumps, the one MIPS rule that surprises every RISC-V reader (the instruction after a branch always runs), then functions and stack frames, followed step by step on a real recursive program.

5. Control flow: branches, jumps and the delay slot

35 min

6. Functions: jal, jr $ra and the stack frame

25 min

4 · Last

HI/LO, the release-2 extras, and the whole toolchain

Multiply and divide through the accumulator, the instructions GCC likes since release 2, and the path from hello.c to words in memory — ending with how an out-of-order engine describes MIPS beside RISC-V.

7. Multiply and divide: HI and LO

18 min

8. Release 2 extras the compiler likes

18 min

9. From C to running MIPS

38 min

Cheat sheet

One page: the three formats as bit layouts, the 32 registers and their o32 jobs, all 63 instructions with what they do, and the rules that catch a RISC-V reader.

Glossary

Every term the book defines, each with an ordinary-words meaning beside the precise MIPS one, and where it was first used.

If you know RISC-V

Every section ends with a “Compared with RISC-V” box: what transfers unchanged, what differs, and which difference would produce a bug. The biggest one is the branch delay slot in §5.4.

Written for one reader, grounded in the MIPS32 Architecture For Programmers (Vol. I–II, MIPS Technologies) and in the Carolyne project's executable MIPS32 description. Every “what the compiler writes” example is copied from real mipsel-linux-gnu-gcc output, with its address.