Fine-grained inter-thread communication is the bane of irregular GPU code. Today’s options are grim: coarsen everything behind barriers (rewrite your algorithm) or hand-build fine-grained locks out of single-word atomics (too risky for shipping software — recall SIMT deadlock). Transactional memory offers a third way: mark a region atomic, let the hardware detect and resolve conflicts. The research question is whether TM can survive the GPU’s scale.
The GPU TM problem
Multicore TM juggles tens of largish transactions and leans on cache coherence to spot conflicts. A GPU flips every assumption: tens of thousands of tiny transactions, tracked at word granularity, on per-core caches shared by hundreds of threads — so coherence-based detection is nearly useless. New mechanisms required.
5.3.1 Kilo TM
. To validate, a transaction simply re-reads its read-set from global memory and checks the values — no global metadata, finest granularity, riding the parallel memory system. Conflicting transactions never touch each other.Value-based conflict detection value-based conflict detectionValidate by re-reading a transaction's read-set from memory and comparing values — no global metadata, finest granularity.Glossary →- The
. Naive value-based detection forces serial commits; the recency bloom filter compresses committing transactions’ write-sets (using time and order) so each committer gets an approximate conflicting set — false positives allowed — enabling hundreds of non-conflicting transactions to commit in parallel. It stays a few kB, on-chip.recency bloom filter recency bloom filterTime-ordered bloom filter compressing committing write-sets so hundreds of non-conflicting transactions commit in parallel (few kB, on-chip).Glossary →
Aborts are a new kind of divergence
When a warp reaches tx_commit, some threads validate and some abort — the
warp diverges after commit. Kilo TM handles this with a small, elegant
extension to the SIMT stack: two new entry types, R
(transaction Retry — records how to restart) and T (Transaction top —
the current attempt), alongside ordinary N (Normal) entries. Step
through one transaction where two of eight threads must retry (Fig 5.2):
Control-flow graph
SIMT stack (TOS on top)
Warp lanes over time
| A | B | C | D | E | F | C' | F' | G | H | |
|---|---|---|---|---|---|---|---|---|---|---|
| t0 | ||||||||||
| t1 | ||||||||||
| t2 | ||||||||||
| t3 | ||||||||||
| t4 | ||||||||||
| t5 | ||||||||||
| t6 | ||||||||||
| t7 |
time →
event 1/8tx_begin. The if() let 6 of 8 threads in (lanes 4–5 skipped to H). Entering the transaction pushes TWO special entries: an R (Retry) entry — how to restart, PC = the instruction after tx_begin (C), mask empty for now — and a T (Transaction-top) entry that copies the active mask (11110011) and tracks the current attempt.
Notice what the R/T mechanism buys: the winners commit once and move on, while only the losers loop back through the implicit abort edge — and ordinary branch divergence inside the transaction still uses plain N entries. The entire TM abstraction rides on the stack the GPU already had.
5.3.2 WarpTM and temporal conflict detection
Fung & Aamodt’s follow-up adds two efficiency wins:
exploits the spatial locality of threads within a warp. A two-phase parallel intra-warp conflict resolution clears conflicts among a warp’s own transactions first; once resolved, their scalar validation/commit accesses coalesce into wide memory operations — finally feeding the vector-width memory system the way it wants to be fed.WarpTM WarpTMWarp-level transaction management: two-phase intra-warp conflict resolution enabling coalesced validation/commit memory accesses.Glossary → (TCD) targets read-only transactions (common in data- structure traversals). Globally synchronized on-chip timers — each running locally, never communicating (the trait that distinguishes TCD from software timestamp schemes) — let Kilo TM infer read ordering and commit conflict-free read-only transactions without any value re-reads, slashing their memory-bandwidth cost.Temporal conflict detection temporal conflict detection (TCD)Implicitly synchronized on-chip timers timestamp reads so conflict-free read-only transactions commit without value checks.Glossary →
| Value-based conflict detection | No usable coherence on GPUs | Re-read read-set from memory; compare values |
| Recency bloom filter | Serial commit bottleneck | Time-ordered compression of write-sets → approximate conflict sets |
| R/T stack entries | Warp diverges after validation | Retry + Transaction-top entries on the SIMT stack |
| WarpTM | Scalar TM accesses waste the wide memory system | Two-phase intra-warp resolution → coalesced validate/commit |
| Temporal conflict detection | Read-only transactions re-read needlessly | Implicitly-synchronized on-chip timers infer read ordering |
Check yourself
1. How does GPU transactional memory differ from CPU/multicore TM in scale?
2. What is value-based conflict detection?
3. What does the recency bloom filter buy Kilo TM?
4. Predict the stack (use the animation): at tx_commit, threads 6 & 7 fail validation. What does the hardware do next?
5. Branch divergence INSIDE a transaction (e.g. if(s[t])) is handled how?
6. WarpTM and Temporal Conflict Detection (TCD) each optimize Kilo TM differently. Which pairing is right?