Interactive textbook
General-Purpose Graphics Processor Architectures
Tor M. Aamodt, Wilson Wai Lun Fung & Timothy G. Rogers — Synthesis Lectures on Computer Architecture, Morgan & Claypool, 2018
Almost every idea in this book is something that happens over time: warps stepping through a pipeline, a branch splitting a warp in two and later putting it back together, addresses merging into memory transactions. So the explanations here are animated — you can play, pause, and step one cycle at a time, and watch the reason for each change as it happens.
Every number an animation shows is simulated from its own scenario data, not typed in beside it. Where a model cannot support the conclusion you would naturally draw, it says so rather than letting the numbers imply it.
Your progress
Answer a section's quiz and it will be remembered here, in this browser only.
A path through it
22 sections, about 222 minutes of reading plus the time you spend with the animations. Chapter 4 borrows two ideas from Chapter 3 — instruction replay and affine addresses — so that order reads more smoothly, but each links back where it needs to.
Why the machine exists, and how you talk to it
Everything later depends on these two. Chapter 1 is the argument for building a GPU at all; Chapter 2 is the programming model that sells scalar threads to a vector machine.
1. Introduction
23 min2. Programming Model
24 minInside one core
One SIMT core opened up and rebuilt in three passes, then a long line of research trying to pay less for divergence.
3. The SIMT Core: Instruction and Register Data Flow
76 min- 3.1 One Loop, and the Stack That Makes Threads Look Independent
- 3.1.2–3.1.3 When the Stack Hangs: SIMT Deadlock, Volta, and Choosing a Warp
- 3.2–3.3 Two More Loops: Issuing Early, and the Trouble With Registers
- 3.4.1 What the Stack Costs, and Warp Compaction
- 3.4.2 Running Both Paths at Once, and Meeting Sooner
- 3.4.3–3.4.4 Borrowing From MIMD, and Refusing to Pay for the Stack
- 3.5 Computing the Same Thing Thirty-Two Times
- 3.6 The Biggest Structure on the Chip
Out to memory and back
One memory request followed from the load/store unit to a DRAM row buffer, and the finding that most GPU memory performance is decided before the cache is consulted. Reuses instruction replay from §3.3 and affine addresses from §3.5, and links back to both.
What fitted in neither
Scheduling, alternative ways of expressing parallelism, transactional memory, and sharing a chip with a CPU. This chapter leans on all four before it.
5. Crosscutting Research on GPU Computing Architectures
53 minGlossary
Every term the book defines, each with an ordinary-words meaning beside the precise architectural one, and where it was first used.
If you read only one section
Make it §4.4.1–4.4.5 . Adding a cache made some programs slower, and hit rate turns out not to predict whether caching helps — the idea here most likely to change what you do the next time you read a profiler.
Built as a personal study aid from the book named above, whose argument, ordering, figures and examples it follows. The prose here is original; the book is the authority, and where its text and its figures disagree this site says so rather than choosing quietly.