Reconfigurable Quantum Instruction Set Computers for High Performance Attainable on Hardware

A quantum computer only runs a few built-in two-qubit gates (usually the CNOT), so any richer operation must be stitched from many of them — slow and error-prone — and while richer native gate sets would help, each new gate needs its own painstaking calibration, so they stay lab demos; this paper (HKUST, Alibaba, Tsinghua, Fudan — Zhaohui Yang, Jianxin Chen, Yuan Xie, and colleagues) presents ReQISC, one reconfigurable hardware scheme that realizes any two-qubit gate at the shortest physically possible duration, plus a compiler for it, cutting average two-qubit pulse time about 5 times.

The argument in one glance

Problem

A quantum computer builds everything from a few native gates

A quantum computer can only physically execute a small set of built-in operations, called its native gates or instruction set architecture (ISA). Everything a program does must be compiled into those gates, and the workhorse two-qubit gate is almost always the CNOT (or the closely related CZ). This is limiting because many useful two-qubit operations are not a single CNOT — they have to be stitched together from several CNOTs plus single-qubit rotations. Each gate takes time and adds error, and on today's noisy quantum hardware, where noise already sharply limits how large a program can run reliably, stringing together many gates to build one operation is expensive: it lengthens the circuit, consumes precious coherence time, and accumulates fidelity loss. So one of the clearest paths to higher performance is to expand the ISA with richer two-qubit gates that have higher fidelity and greater "synthesis capability" — meaning a single native gate can directly realize operations that would otherwise need many CNOTs. In principle you could go all the way to the most expressive possible ISA: making every two-qubit gate native. The obstacle is that richer gate sets are far harder to actually build and use on hardware.
What people did

Propose more expressive gate sets, one special gate at a time

Researchers and vendors have proposed many richer two-qubit gates beyond CNOT: Google's Sycamore gate from the fSim family, SQiSW, Rigetti's parametrized XY gates, IBM's fractional-ZZ gates, IonQ's partial Molmer-Sorensen (MS) gates, and others. These continuous gate sets appear to improve fidelity and let circuits be synthesized with fewer gates. At the frontier, some work proposes using the entire space of two-qubit gates as the ISA. Each of these is added to a device as a new native operation, calibrated and then exposed for programs to use.
Why it fell short

Every new gate needs its own calibration and breaks the compiler

Expanding the ISA this way runs into two walls that have kept expressive gate sets as proofs-of-concept rather than mainstream. The first is calibration. A quantum gate is realized by a carefully tuned analog control pulse, and making that pulse do exactly the right operation requires calibration — an experimental tuning process that is slow and must be repeated per gate. A richer ISA means more gates to calibrate, and a continuous gate family means, in effect, infinitely many distinct gates, so the calibration overhead becomes prohibitive. The second wall is compilation. Existing quantum compilers are built around the CNOT-based paradigm; feeding them a large or continuous gate set introduces hard new optimization problems — how to synthesize operations from the new primitives, how to optimize circuits made of them, and how to map and route qubits when the native two-qubit gate is far more capable. Without a compiler that understands the new ISA, its theoretical advantages cannot be realized in practice. So the field was stuck: the most expressive ISAs promise large gains on paper, but each demands per-gate calibration the hardware cannot afford and a compiler the software stack does not have. What was missing was a way to make an arbitrarily-expressive two-qubit ISA both physically realizable without a calibration explosion and usable through an end-to-end compiler.
This paper's idea

One reconfigurable scheme for any gate, plus a compiler that uses it

ReQISC — reconfigurable quantum instruction set computers — makes the most expressive two-qubit ISA practical by tackling both walls at once, as a full-stack co-design of hardware and compiler. Its ISA is the entire space of two-qubit gates: mathematically, all of SU(4), up to cheap single-qubit rotations, which means any two-qubit operation is a native instruction. The first piece is a unified, reconfigurable microarchitecture — a single gate scheme that can directly implement any two-qubit gate, at the theoretically optimal (shortest possible) duration for whatever two-qubit interaction the hardware physically has, using simple pulse controls. Because one reconfigurable scheme covers every gate rather than each gate being a separately-calibrated operation, it sidesteps the calibration explosion. The second piece is a compiler tailored to these primitives, with three passes: a program-aware pass that refines the high-level program representation, a program-agnostic pass that aggressively optimizes at the circuit level, and an SU(4)-aware routing pass that minimizes the overhead of mapping qubits onto the hardware. Together, the expressivity of the full gate space and the optimal gate durations from the microarchitecture yield large gains: a 4.97-times reduction in the average pulse duration needed to implement an arbitrary two-qubit gate versus the usual CNOT/CZ scheme on mainstream flux-tunable transmons, and, end to end, fewer two-qubit gates, shallower circuits, shorter pulses, less qubit-mapping overhead, and lower fidelity loss than a conventional CNOT ISA with a state-of-the-art compiler. For the first time, ReQISC makes the theoretical benefits of continuous ISAs practically feasible.

Why this problem is worth solving

On noisy quantum hardware, everything comes down to doing an operation in as few, as short, and as accurate gates as possible, and the two-qubit gate is where most of the cost lives.

Quantum programs are bottlenecked by noise: every gate takes time during which the fragile quantum state decoheres, and every gate adds a bit of error, so the number and duration of gates directly sets how large and deep a program can run before the answer is swamped by noise. Two-qubit gates are the expensive, error-prone part of this — they are slower and noisier than single-qubit gates, and they dominate the fidelity budget. When the only native two-qubit gate is CNOT, any richer operation must be built from a chain of CNOTs, multiplying the time and error for something the hardware could in principle do in one shot. So expanding the two-qubit ISA to richer gates is not a marginal tuning; it attacks the dominant cost of running quantum programs, potentially shrinking circuits, shortening the time on hardware, and cutting fidelity loss all at once. That is why the field has kept proposing more expressive gate sets. The reason it matters that ReQISC makes them practical is that the theoretical gains have been real but unreachable — blocked by calibration and compilation. Turning “an expressive ISA would help in theory” into “an expressive ISA you can actually calibrate and compile for” is what lets those gains show up on real machines, which is the difference between a promising idea and a performance improvement people can use.

The key realization is that expressivity and practicality can be reconciled by making one gate scheme reconfigurable, rather than adding gates one calibrated instruction at a time.

The historical bind is that expressivity and practicality pulled in opposite directions. To get expressivity you add more native gates; but every native gate is an analog pulse that must be individually calibrated, and a truly expressive, continuous ISA implies effectively infinite gates to calibrate — so more expressivity meant more calibration until it became infeasible. ReQISC breaks that link by changing what a “native gate” is. Instead of treating each desired two-qubit gate as a distinct instruction with its own calibration, it provides a single reconfigurable microarchitecture that, given the hardware’s underlying two-qubit interaction, can be set up on the fly to realize any two-qubit gate — and to do so in the minimum time physically allowed for that interaction. Because the scheme is one mechanism parametrized to produce any gate, rather than a library of separately-calibrated gates, you get the full expressivity of the entire two-qubit gate space without a proportional calibration cost. And because it hits the theoretically optimal duration, each gate spends the least possible time exposed to noise. The remaining half of the problem is that a compiler must actually exploit this: knowing that any two-qubit gate is available and cheap changes how you synthesize, optimize, and route a circuit. So the crux is a co-design — a reconfigurable gate scheme that makes the expressive ISA physical, paired with a compiler built to use it — which is exactly what turns the theoretical benefit into a measured one.

What people did before, and where it broke

Use a CNOT-based ISA. Make CNOT (or CZ) the only native two-qubit gate and build everything from it. Where it broke. Rich operations need many CNOTs, lengthening circuits and accumulating time and error on noisy hardware.
Add specific richer gates (fSim, SQiSW, XY, fractional-ZZ, partial MS). Introduce particular higher-fidelity two-qubit gates for certain applications. Where it broke. Each is a separate native gate needing its own calibration, and general compilers are not built to exploit them, so adoption stays narrow.
Propose the full continuous gate set as the ISA. Aim for the most expressive possible two-qubit instruction set. Where it broke. A continuous family means effectively infinite gates to calibrate, and no end-to-end compiler exists for it, so it stays a proof-of-concept.
Compile expressive circuits with CNOT-era tools. Reuse existing transpilers on the richer gate set. Where it broke. They are built around CNOT and cannot synthesize, optimize, or route efficiently for a maximally-expressive two-qubit ISA.
The gap. No approach made an arbitrarily-expressive two-qubit ISA both calibratable without an explosion and usable through an end-to-end compiler, so the theoretical benefits of continuous ISAs went unrealized.

How ReQISC works

From per-gate calibration to a reconfigurable scheme plus a matching compiler

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The idea

Give the machine the richest possible gate vocabulary so circuits shrink. ReQISC adopts the full two-qubit gate space as its ISA, so any two-qubit operation is one native gate rather than a chain of CNOTs, producing shorter, shallower, higher-fidelity circuits. Aggressively reducing the size and cost of a quantum circuit by giving the compiler richer building blocks and better options to synthesize from is the same goal the work on optimizing quantum circuits fast and slow (fast-and-slow optimization) covered elsewhere on this site pursues, squeezing circuits down to fewer, cheaper operations. ReQISC pushes this to the limit by making every two-qubit gate directly available.

Realize the gate at the pulse level, at optimal time, without a calibration blowup. The reconfigurable microarchitecture implements any two-qubit gate through simple pulse controls at the theoretically minimal duration for the hardware’s interaction, so gates are as fast and low-noise as physics allows. Engineering the low-level pulse control of a superconducting two-qubit gate to raise its fidelity and reduce the error it accumulates is the same concern the work on suppressing ZZ crosstalk through pulse and scheduling optimization (ZZ crosstalk suppression) covered elsewhere on this site addresses, treating pulse-level control as the lever for better gates. ReQISC’s scheme is a reconfigurable pulse recipe that yields any gate at optimal duration rather than a fixed set of separately-tuned gates.

Build a compiler that exploits the new ISA, including smarter routing. ReQISC pairs the hardware with an end-to-end compiler whose SU(4)-aware routing minimizes the overhead of mapping qubits onto the device, because a more capable native gate changes how circuits should be laid out. Reducing the qubit-mapping and routing overhead that a naive compiler would incur, by having the compiler understand what the hardware can natively do, is the same lever the work on compiler-assisted qubit reuse through dynamic circuits (CAQR) covered elsewhere on this site pulls, cutting the resource cost of running a circuit on real hardware. ReQISC’s routing pass is co-designed with its expressive ISA to keep mapping overhead low.

Following a two-qubit operation through ReQISC

Running an arbitrary two-qubit operation

A trace, drawn from the paper, of how ReQISC realizes and compiles a two-qubit gate.

Step 1 of 5

The program needs an arbitrary two-qubit gate

A quantum program calls for some two-qubit operation that, on a CNOT machine, would be synthesized from several CNOTs and single-qubit rotations.

On CNOT hardware this is a multi-gate, multi-pulse sequence.

Why it works

A richer native gate replaces many CNOTs. Any two-qubit operation on a CNOT machine needs several CNOTs → but making the whole two-qubit gate space native → so one instruction does what previously took a chain, cutting gate count and depth.
A reconfigurable scheme avoids the calibration explosion. A continuous gate set would need effectively infinite per-gate calibration → but one reconfigurable microarchitecture parametrized to produce any gate → so expressivity comes without proportional calibration cost.
Optimal-duration gates minimize exposure to noise. Longer pulses decohere and accumulate error → but implementing each gate at the theoretically shortest time for the coupling → so average two-qubit pulse duration drops about 4.97 times and fidelity loss falls.
A tailored compiler turns capability into circuits. An expressive ISA is useless if the compiler cannot exploit it → but program-aware, program-agnostic, and SU(4)-aware routing passes → so the hardware’s power actually reduces gates, depth, and mapping overhead.
Co-designing hardware and compiler realizes the theory. Either piece alone leaves the gains stranded → but pairing the reconfigurable microarchitecture with a matching compiler → so the long-promised benefits of continuous ISAs finally appear on real hardware.

What it costs (trade-offs and scope)

It requires a reconfigurable microarchitecture and pulse control. ReQISC’s benefits depend on hardware that supports the reconfigurable gate scheme and its pulse controls; it is a hardware-software co-design, not a software-only change to existing machines.
It is tied to the hardware’s coupling Hamiltonian. The optimal durations are optimal given the device’s two-qubit interaction; the scheme is demonstrated on flux-tunable transmons, and other platforms would need the microarchitecture instantiated for their physics.
The compiler must be adopted alongside the ISA. The end-to-end gains require the tailored compiler passes; using the expressive ISA with a CNOT-era compiler would leave much of the benefit unrealized.
Calibration is reduced, not eliminated. The reconfigurable scheme avoids per-gate calibration of a continuous family, but the microarchitecture itself must still be characterized and controlled accurately.
Reported figures are on specific hardware and baselines. The 4.97-times pulse-duration reduction and the end-to-end improvements are measured against the CNOT/CZ scheme and a state-of-the-art compiler on mainstream flux-tunable transmons; results depend on the platform, circuits, and baselines.

The comparison

Choosing a two-qubit instruction set and how to realize it

Property	CNOT-based ISA	Specific richer gates	ReQISC
Native two-qubit gates
Calibration cost
Gate duration
Compiler support
Practically adopted

A comparison of two-qubit instruction sets. A CNOT-based ISA is mature but synthesizes rich operations from many gates; specific richer gates help but each needs its own calibration and lacks compiler support. ReQISC makes the full two-qubit gate space (SU(4)) native via one reconfigurable microarchitecture at optimal gate duration, with a matching end-to-end compiler — cutting average two-qubit pulse duration about 4.97 times on flux-tunable transmons and reducing gate count, depth, mapping overhead, and fidelity loss. Exact figures should be read from the paper.Underlined values explain themselves when clicked.

Where this stops working

What to keep in mind

This explainer is based on the paper’s full text (the authors’ arXiv copy, 2511.06746, of the ASPLOS 2026 paper). The described system is the paper’s: ReQISC (reconfigurable quantum instruction set computers) is a full-stack co-design that makes an expressive continuous two-qubit ISA practical. It uses the entire two-qubit gate space as its ISA — all of SU(4), modulo single-qubit rotations — and comprises (1) a unified, reconfigurable microarchitecture that can directly implement any two-qubit gate at theoretically optimal duration given the hardware’s two-qubit coupling Hamiltonian, via simple pulse controls, and (2) a compilation framework with a program-aware pass, a program-agnostic circuit-optimization pass, and an SU(4)-aware routing pass that minimizes qubit-mapping overhead. The paper reports a 4.97-times reduction in average pulse duration to implement arbitrary two-qubit gates versus the CNOT/CZ scheme on mainstream flux-tunable transmons (and cites prior experimental SU(4) fidelity around 99.37 percent), and, end to end, reductions in two-qubit gate count, circuit depth, pulse duration, qubit-mapping overhead, and program fidelity loss versus a conventional CNOT ISA with a state-of-the-art compiler and pulse implementation. The background above on native gates, ISAs, CNOT, SU(4), gate calibration, pulses, and qubit routing is standard context provided to make the approach intuitive. The step-by-step walkthrough is an illustration of the described mechanism. Exact microarchitecture, pulse and calibration details, the compiler passes, and the full evaluation should be read from the paper.

Background

Why quantum performance keeps hinging on co-designing the gate set with the stack

It helps to see ReQISC within a broad theme in quantum computing: the performance a program actually achieves is set less by any single layer than by how well the layers are co-designed, and the choice of instruction set sits right at the seam between hardware physics and the compiler. On noisy machines, every gate is expensive, so the whole stack is a fight to express a computation in the fewest, shortest, most accurate operations the hardware allows. That fight recurs at every level — synthesizing circuits, optimizing them, mapping and routing qubits, and controlling the analog pulses that realize gates — and progress usually comes from a layer being redesigned with knowledge of the layers around it rather than in isolation. The instruction set is a particularly powerful lever because it determines, in one stroke, both what the hardware must physically build and calibrate and what the compiler has to work with. ReQISC is a clean instance of co-designing that lever: it picks the most expressive possible two-qubit ISA, makes it physically affordable with a reconfigurable optimal-time gate scheme, and builds the compiler to exploit it. This drive to squeeze quantum performance by optimizing across the compilation stack rather than one gate at a time is the same terrain the work on a generalized block-wise compiler optimization framework for quantum programs (Paulihedral) covered elsewhere on this site occupies, co-optimizing structure across layers. ReQISC’s particular contribution is to show that, by co-designing an expressive ISA with a reconfigurable microarchitecture and a matching compiler, the long-theorized benefits of continuous gate sets can finally be realized on real hardware.

If you remember only three things

1. A quantum computer can only physically run a small set of native gates (its instruction set), and the workhorse two-qubit gate is almost always the CNOT, so any richer two-qubit operation must be stitched from several CNOTs plus single-qubit rotations — lengthening circuits and accumulating time and error on noisy hardware where two-qubit gates dominate the fidelity budget. Expanding the instruction set with richer, higher-fidelity two-qubit gates would let one native gate do what previously took many, but this has stayed a proof-of-concept because of two walls: every new gate needs its own slow experimental calibration (and a continuous gate family means effectively infinite gates to calibrate), and existing compilers are built around CNOT and cannot synthesize, optimize, or route for an expressive gate set.
2. ReQISC (reconfigurable quantum instruction set computers) makes the most expressive two-qubit ISA — the entire space of two-qubit gates, SU(4), up to cheap single-qubit rotations — practical by co-designing hardware and compiler. Its reconfigurable microarchitecture is a single gate scheme that, given the hardware's two-qubit interaction, can be set to implement any two-qubit gate at the theoretically shortest possible duration using simple pulse controls, so it delivers full expressivity without calibrating each gate separately. Its tailored compiler has a program-aware pass, an aggressive program-agnostic circuit-optimization pass, and an SU(4)-aware routing pass that minimizes qubit-mapping overhead, so the hardware's capability actually turns into shorter, shallower, more accurate circuits.
3. By combining the expressivity of the full two-qubit gate space with optimal gate durations and a matching compiler, ReQISC reports a 4.97-times reduction in the average pulse duration to implement an arbitrary two-qubit gate versus the CNOT/CZ scheme on mainstream flux-tunable transmons, and end-to-end reductions in two-qubit gate count, circuit depth, pulse duration, qubit-mapping overhead, and fidelity loss versus a conventional CNOT ISA with a state-of-the-art compiler — making continuous ISAs practically feasible for the first time. The trade-offs and scope: it requires a reconfigurable microarchitecture with pulse control, is tied to the hardware's coupling Hamiltonian (demonstrated on flux-tunable transmons), needs its compiler adopted alongside the ISA, and reduces rather than eliminates calibration. This explainer is based on the paper's full text.

Check yourself

Check your understanding

1. Why does relying on the CNOT as the only native two-qubit gate limit quantum performance?
2. Why have more expressive (continuous) two-qubit gate sets stayed proofs-of-concept?
3. What are ReQISC's two co-designed pieces, and how do they overcome those walls?
4. What does ReQISC achieve, and what are the limits of the approach?

Sources

The paper is “Reconfigurable Quantum Instruction Set Computers for High Performance Attainable on Hardware” by Zhaohui Yang, Dawei Ding, Qi Ye, Cupjin Huang, Jianxin Chen, and Yuan Xie (The Hong Kong University of Science and Technology, Fudan University and the Shanghai Institute for Mathematics and Interdisciplinary Sciences, Tsinghua University, and DAMO Academy, Alibaba Group), published at ASPLOS 2026, DOI 10.1145/3779212.3790208. It is available on arXiv as 2511.06746.

This explainer is written from the paper’s full text (the authors’ arXiv copy). ReQISC makes an expressive continuous two-qubit ISA practical by co-designing a reconfigurable microarchitecture that implements any two-qubit gate (all of SU(4), up to single-qubit rotations) at theoretically optimal duration via simple pulse controls, with an end-to-end compiler (program-aware, program-agnostic, and SU(4)-aware routing passes). The paper reports a 4.97-times reduction in average two-qubit pulse duration versus the CNOT/CZ scheme on flux-tunable transmons and end-to-end reductions in gate count, depth, pulse duration, mapping overhead, and fidelity loss versus a conventional CNOT ISA with a state-of-the-art compiler. Background on native gates, ISAs, CNOT, SU(4), calibration, and qubit routing is standard context. The numbers are the paper’s own; exact mechanisms and full results should be confirmed in the paper.