ASPLOS, explained

Training and serving neural networks: schedulers, parallelism strategies, LLM inference, ML frameworks and compilers.

Irregular, pointer-chasing workloads: graph analytics and mining engines, traversal frameworks, and graph neural networks.

Domain-specific hardware: NPUs, systolic arrays, FPGAs, ASICs, and the compilers and interfaces that drive them.

GPU architecture, kernels, and runtimes: warp scheduling, occupancy, CUDA, and multi-GPU systems.

The memory hierarchy: caches, coherence, prefetching, DRAM, virtual memory, TLBs, and CXL-attached memory.

Computing where the data lives, and beyond-CMOS substrates: PIM, ReRAM crossbars, photonics, analog and DNA storage.

Durable data: SSDs and flash translation layers, file systems, key-value stores, and persistent memory.

Kernels and the machines they pretend to be: syscalls, schedulers, containers, hypervisors, and unikernels.

From source to machine: IRs and code generation, JITs, DSLs, type systems, and program synthesis.

Getting many threads to agree: synchronization, lock-free structures, memory models, and race detection.

Defending the stack: side channels, speculative execution attacks, enclaves, memory safety, and encrypted computation.

Warehouse-scale systems: serverless, microservices, RPC and RDMA, cluster scheduling, and resource management.

Quantum architecture and toolchains: qubit mapping, error correction, pulse control, and quantum compilers.

The cost of computing in watts and carbon: power management, thermal limits, and embodied emissions.

Making systems trustworthy: formal verification, fuzzing, bug finding, fault tolerance, and debugging tools.

Computing at the edge: smartphones, AR/VR, IoT and batteryless devices, robotics and autonomous vehicles.