PACT: A Criticality-First Design for Tiered Memory

Tiered memory keeps a small fast tier (DRAM) and a big slow tier (like CXL), and decides which pages go where by how often each page is touched — but a page touched a million times in a fast streaming loop hurts far less than one touched rarely in a pointer-chase, because the CPU can hide the streaming latency; this paper (Virginia Tech — Hamid Hadian, Huaicheng Li, and colleagues) presents PACT, which measures each page's actual contribution to CPU stalls online from four hardware counters and places pages by that, running up to 61 percent faster than the best prior system with up to 50 times fewer migrations.

The argument in one glance

Problem

Tiered memory places pages by how often they are touched

As DRAM stops getting cheaper per byte while memory-hungry workloads keep growing, datacenters increasingly pair a small, fast tier of DRAM with a larger, slower tier — NUMA-remote memory, persistent memory, or, increasingly, memory attached over Compute Express Link (CXL), which lets memory be pooled and shared across machines. The catch is that the slow tier has meaningfully higher access latency: CXL memory is roughly 2 to 3 times slower to reach than local DRAM. So a tiered memory system constantly faces one decision: which pages should live in the scarce fast DRAM, and which can be left in the slow tier? The near-universal answer today is hotness — put the pages that are accessed most frequently (or most recently) into DRAM, on the assumption that frequently-accessed pages are the ones whose speed matters most to the application. Systems sample memory accesses, count per-page access frequency, and migrate the hottest pages up. This is intuitive and simple, and it is the basis of essentially all deployed tiering designs. But it rests on an assumption — that frequency equals performance importance — that turns out not to hold.
What people did

Assume the most-accessed pages are the most performance-critical

The standard approach treats access frequency as a stand-in for performance impact: sample accesses, rank pages by how hot they are, and keep the hottest ones in fast memory. More recent work noticed that hotness is imperfect and tried to add a notion of criticality — but did so either with offline, coarse-grained profiling (attributing cost at the level of whole data objects, computed ahead of time) or by using criticality only as a secondary, reactive hint layered on top of a placement policy that is still fundamentally driven by hotness. In both cases, the machinery still fundamentally decides placement by how often pages are touched.
Why it fell short

Frequency does not equal the performance cost of an access

Hotness is an unreliable proxy because the real thing that matters — how much a slow-tier access actually costs the CPU in stall time — depends on far more than frequency. Modern out-of-order CPUs hide memory latency by issuing many memory requests concurrently, a property called memory-level parallelism (MLP). Consider two pages accessed the exact same number of times. One is read during a sequential array traversal, where the CPU can have many outstanding requests at once, so the slow-tier latency is overlapped and amortized — the page barely hurts performance even in the slow tier. The other is read during pointer chasing, where each access depends on the previous one, so requests are serialized and every access exposes the full memory latency — this page stalls the CPU badly if it is slow. Same frequency, wildly different performance cost. Frequency-based tiering cannot tell these apart, so it wastes precious DRAM on hot-but-latency-tolerant pages while leaving cold-but-critical pages stranded in slow memory. The prior criticality-aware attempts do not fix this: offline object-level profiling lacks the page-level precision and the online adaptability to track how criticality shifts as a program runs through different phases, and using criticality as a mere hint keeps hotness in charge. What was missing was a system that measures each page's true, online, per-page contribution to CPU stalls and places pages by that — making criticality, not frequency, the first-class driver.
This paper's idea

Measure each page's real stall cost online and place by that

PACT is a tiered memory design built around performance criticality as a first-class principle. Its core is Per-page Access Criticality (PAC): a metric that quantifies how much each individual page contributes to the CPU's stall time, rather than merely counting its accesses. The challenge is estimating this online without special hardware, since the CPU's stall counters are coarse — per-core aggregates that mix together accesses to all memory tiers. PACT overcomes this with a lightweight analytical model, grounded in a study of 96 workloads, that models per-tier CPU stalls as a function of last-level-cache misses, latency, and MLP (fitting with a correlation above 0.98), and — its key trick — decomposes memory-level parallelism per tier by reading hardware queue-occupancy counters (from the CPU's on-chip request queues), which via Little's Law lets it attribute stall time to the fast versus slow tier and, within a short time window, down to individual pages. Because workloads hold stable execution phases for tens of milliseconds before shifting, this attribution stays accurate while still adapting online. Building on PAC, and because the distribution of criticality across pages is highly skewed (a few pages dominate the stalls), PACT uses two PAC-centric migration policies: eager demotion, which proactively pushes low-criticality pages down to free fast-tier space so critical pages can be promoted promptly, and adaptive promotion, which uses lightweight statistical sampling with adaptive binning to spot high-PAC pages without global sorting or hand-tuned thresholds. Across 13 workloads and against 7 state-of-the-art tiering systems, PACT is up to 61 percent faster than the best of them, with up to 50 times fewer migrations.

Why this problem is worth solving

Tiered memory is how datacenters cope with the growing gap between compute demand and affordable DRAM, so getting page placement right directly determines how much that hardware delivers.

The economics are forcing the issue: DRAM is no longer scaling down in cost per byte the way it once did, while workloads — graph analytics, in-memory caches, machine learning — keep demanding more memory. The response is to mix a fast, expensive DRAM tier with a cheaper, slower tier, and CXL is accelerating this by letting memory be disaggregated and pooled across a rack. But the slow tier is 2 to 3 times slower to access, so where each page lives has a real and continuous effect on performance. Because the fast tier is scarce, you cannot keep everything there; you must choose, and choose continuously as the workload changes. A better placement policy is therefore not a marginal tuning — it decides how much of the promised capacity savings you get to keep without paying a performance penalty. For performance-sensitive applications running on tiered or CXL memory, the placement decision is the whole ballgame, which is why the field has invested so heavily in sampling, migration, and hotness-tracking machinery. The lever PACT pulls — deciding placement by true performance cost — acts on exactly this decision, so improving it improves the fundamental value proposition of tiered memory.

The crux is that the signal everyone uses, access frequency, is measuring the wrong thing, and the fix is to measure the right thing directly.

The appeal of hotness is that it is easy to measure — you just count accesses — and it feels like a good proxy for importance. But the quantity that actually determines whether a page should be in fast memory is how much the application slows down when that page is slow, and modern CPUs sever the link between access count and slowdown. Through out-of-order execution and memory-level parallelism, a CPU can overlap many concurrent slow accesses so they cost almost nothing, or it can stall fully on a single serialized one. So a page hammered by a streaming loop may be latency-tolerant, while a rarely-touched page on a pointer-chasing critical path may be the true bottleneck. Counting accesses cannot distinguish them; only measuring the stall cost can. PACT’s insight is to stop inferring importance from an indirect proxy and instead quantify each page’s contribution to CPU stalls directly and online. The reason this is hard, and the reason it had not been done at page granularity before, is that the hardware does not hand you per-page, per-tier stall time — the counters are coarse aggregates. PACT’s contribution is showing that a careful analytical model over four standard counters, decomposing parallelism per tier, recovers that missing precision, turning a better-in-principle idea into a practical, deployable one.

What people did before, and where it broke

Place pages by access frequency (hotness). Sample accesses, rank pages by how often they are touched, and keep the hottest in DRAM. Where it broke. Frequency does not equal performance cost — a high-MLP streaming page hurts little in slow memory, while a low-MLP pointer-chasing page hurts a lot, so hotness misplaces pages.
Use recency alongside frequency. Promote recently-accessed pages too. Where it broke. Still a frequency-style proxy; it does not capture how much an access actually stalls the CPU.
Add criticality via offline, coarse-grained profiling. Attribute performance cost ahead of time at the level of whole data objects. Where it broke. It lacks per-page precision and cannot adapt online as criticality shifts across a program’s execution phases.
Treat criticality as a reactive hint atop hotness policies. Layer a criticality signal on top of a fundamentally hotness-driven placement engine. Where it broke. Hotness still drives the decisions, so criticality is never a first-class principle and the placement stays frequency-led.
The gap. No system measured each page’s true, online, per-page contribution to CPU stalls and made that the primary driver of placement — so none could reliably keep the genuinely performance-critical pages, and only those, in fast memory.

How PACT works

From counting accesses to measuring per-page stall cost

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The idea

Judge a page by whether it is on the performance-critical path, not by how often it is touched. PACT’s foundation is that the pages worth putting in fast memory are the ones whose slow accesses actually stall the CPU, which — because of memory-level parallelism — is not the same as the most-accessed pages. Focusing effort on the specific memory accesses that lie on the critical path of execution, rather than treating all frequent accesses as equally important, is the same principle the work on critical slice prefetching (CRISP) covered elsewhere on this site is built on, singling out the accesses that truly gate progress. PACT brings that critical-versus-frequent distinction to page placement, quantifying each page’s criticality instead of assuming frequency stands in for it.

Estimate the right signal cheaply and online from ordinary counters. For criticality to drive a live system, PACT must compute each page’s stall contribution transparently, without app changes or special hardware, so it builds a lightweight analytical model over just four standard CPU performance counters and runs it continuously in the background. Making memory-management decisions in the datacenter transparently and online from lightweight runtime signals, rather than demanding offline profiling or program changes, is the same approach the work on transparent memory offloading in datacenters (TMO) covered elsewhere on this site takes, letting the system react to real behavior as it happens. PACT’s per-tier MLP decomposition is what makes its signal, CPU-stall contribution, both accurate and cheap enough to use this way.

Drive tiered-memory migration with the better signal. Ultimately PACT is a page placement engine for tiered and CXL memory: it decides which pages to promote to DRAM and which to demote, using eager demotion and adaptive promotion tuned to criticality’s skew. Transparently placing and migrating pages across a fast and slow tier to get the performance of DRAM at the capacity of a cheaper tier is the same enterprise the work on transparent page placement for CXL-enabled tiered memory (TPP) covered elsewhere on this site pursues, deciding placement without application involvement. PACT advances that enterprise by replacing the hotness signal at its heart with directly-measured performance criticality, which is what lets it move far fewer pages while performing better.

Following a page through PACT

Deciding where a page belongs by its stall cost

A trace, drawn from the paper, of how PACT quantifies a page's criticality and acts on it.

Step 1 of 5

Two equally-hot pages behave very differently

Suppose two pages are accessed the same number of times: one during a sequential array traversal (high memory-level parallelism), one during pointer chasing (serialized, low parallelism). A hotness-based system sees them as equally important.

Frequency alone cannot tell that one is far more latency-sensitive.

Why it works

Stall cost is what performance actually depends on. Access frequency does not track how much a page slows the CPU → but measuring each page’s contribution to stall time directly → so placement optimizes the quantity that truly determines performance.
Per-tier MLP decomposition recovers hidden precision. Raw CPU counters aggregate stalls across all tiers per core → but decomposing memory-level parallelism per tier via queue-occupancy counters and Little’s Law → so PACT can attribute stalls to the slow tier and to individual pages.
Phase stability makes online per-page attribution valid. Attributing stall time to pages continuously could be noisy → but workloads hold stable MLP phases for tens of milliseconds → so within a window, per-page attribution is accurate while still adapting as phases shift.
Skew means moving a few pages captures most of the benefit. Migrating many pages is costly and mostly wasted → but criticality is highly skewed onto a few pages → so promoting just those, via adaptive binning, gets the gain with up to 50 times fewer migrations.
Eager demotion removes the promotion bottleneck. Critical pages cannot be promoted if the fast tier is full → but proactively demoting low-PAC pages to free space → so high-criticality pages reach DRAM promptly instead of waiting.

What it costs (trade-offs and scope)

PAC is an estimate from an analytical model, not ground truth. The per-page stall attribution comes from modeling four counters and decomposing MLP per tier; it fits well (correlation above 0.98 in the study) but remains a model, so its accuracy bounds the quality of placement.
It relies on the right hardware counters. PACT reads standard performance counters including queue-occupancy signals from the CPU’s request queues; the approach depends on those counters being available and meaningful on the target hardware.
It assumes phase stability holds. The online per-page attribution is justified by workloads holding stable MLP phases for tens of milliseconds; workloads that change behavior far faster than that would stress the model’s assumptions.
It targets page placement, transparently. PACT operates without application changes and improves tiering decisions; it is not changing the application’s algorithms or the hardware, so its gains are bounded by how much better placement can help a given workload.
Reported figures are against specific baselines and settings. The up-to-61-percent speedup and up-to-50-times-fewer-migrations are measured across 13 workloads and 7 prior systems at various tier ratios; when not best, PACT trails the top baseline by 4.1 percent on average (11.8 percent at most), and exact gains depend on the workload and configuration.

The comparison

Choosing which pages live in fast tiered memory

Property	Hotness-based tiering	Criticality as a hint	PACT
Placement signal
Accounts for MLP / pattern
Granularity and timing
Migration volume
Performance

A comparison of ways to decide which pages belong in fast tiered memory. Hotness-based systems place by access frequency, which ignores that memory-level parallelism lets the CPU hide the latency of some accesses; adding criticality as a reactive hint leaves frequency in charge. PACT measures each page's true contribution to CPU stalls online from four hardware counters and places by that, running up to 61 percent faster than the best of 7 state-of-the-art systems across 13 workloads while performing up to 50 times fewer migrations. Exact figures should be read from the paper.Underlined values explain themselves when clicked.

Where this stops working

What to keep in mind

This explainer is based on the paper’s full text (the authors’ copy hosted at Virginia Tech). The described system is the paper’s: PACT is an online, page-granular tiered memory design that makes performance criticality a first-class principle. Its core metric, Per-page Access Criticality (PAC), quantifies each page’s contribution to CPU stall time rather than counting accesses. PACT estimates PAC online using a lightweight analytical model — derived from a study of 96 workloads — that models per-tier CPU stalls as a function of last-level-cache misses, latency, and memory-level parallelism (reported Pearson correlation above 0.98), uniquely decomposing per-tier MLP via hardware queue-occupancy counters (the paper references the CPU’s CHA/TOR queues) and Little’s Law, using only four standard CPU performance counters; it relies on workloads holding stable execution phases (tens of milliseconds) to attribute per-tier stall time to individual pages. To handle highly skewed PAC distributions, PACT uses eager demotion (proactively freeing fast-tier space) and adaptive promotion (lightweight sampling with adaptive binning, avoiding global sorting or static thresholds). Evaluated on 13 memory-intensive workloads against 7 state-of-the-art tiering systems (the paper names Soar, Alto, Memtis, Colloid, Nomad, TPP, and Linux NUMA Balancing Tiering) across 7 tier ratios, PACT reports up to 61 percent improvement over the second-best system, an average gap of 4.1 percent (maximum 11.8 percent) when it is not top, and up to 50 times fewer migrations. PACT is open-source. Background on tiered memory, CXL, hotness-based placement, memory-level parallelism, and Little’s Law is standard context. The step-by-step walkthrough is an illustration of the described mechanism. Exact model details, the migration algorithms, and the full evaluation should be read from the paper.

Background

Why the memory hierarchy keeps forcing the question of what to keep close

It helps to see PACT within a long line of work on heterogeneous and tiered memory. The enduring problem is that fast memory is scarce and expensive while capacity demand is unbounded, so systems must keep a fast tier and a slow tier and continuously decide what belongs where — and CXL has made this sharper by turning memory into a disaggregated, poolable resource with its own latency penalty. Much of the field’s progress is about the signal that drives this decision: how do you know, cheaply and in time, which data is worth the fast tier? The default answer has long been recency and frequency, inherited from decades of caching intuition, and it works until the thing you actually care about — end-to-end performance — stops correlating with access counts, which is exactly what modern latency-hiding CPUs cause. PACT is a clean instance of upgrading the signal: it keeps the transparent, online, migrate-in-the-background structure of a tiering system but replaces hotness with a direct measurement of performance cost. The broader setting it operates in — building CXL-based tiered and pooled memory that gives cloud platforms DRAM-like performance at lower cost and higher capacity — is the same terrain the work on CXL-based memory pooling systems for cloud platforms (Pond) covered elsewhere on this site occupies, making disaggregated memory practical to deploy. PACT’s particular contribution is to show that measuring per-page criticality online, from ordinary CPU counters, and placing pages by it, beats frequency-based tiering substantially while moving far less data.

If you remember only three things

1. Tiered memory pairs a small, fast DRAM tier with a larger, slower tier (NUMA, persistent memory, or CXL, which is roughly 2 to 3 times slower), and must continuously decide which pages live in DRAM. Essentially all deployed systems decide by hotness — access frequency — assuming the most-touched pages matter most. But frequency is a poor proxy for performance impact, because modern out-of-order CPUs hide memory latency through memory-level parallelism: a page streamed in a sequential loop (high parallelism) can tolerate slow-tier latency almost for free, while a rarely-touched page on a pointer-chasing path (serialized, low parallelism) stalls the CPU badly. Two equally-hot pages can thus impose wildly different costs, so hotness-based tiering wastes DRAM on latency-tolerant pages and strands genuinely critical ones.
2. PACT makes performance criticality a first-class principle. Its metric, Per-page Access Criticality (PAC), quantifies each page's contribution to CPU stall time rather than counting accesses. The hard part is estimating this online without special hardware, since CPU stall counters are coarse per-core aggregates that mix all tiers; PACT solves it with a lightweight analytical model (from a 96-workload study) that predicts per-tier stalls from last-level-cache misses, latency, and MLP with correlation above 0.98, decomposing memory-level parallelism per tier via hardware queue-occupancy counters and Little's Law, using just four standard counters — and it leverages the fact that workloads hold stable execution phases for tens of milliseconds to attribute stall time to individual pages. Because criticality is highly skewed onto a few pages, PACT uses eager demotion (proactively freeing fast-tier space) and adaptive promotion (lightweight sampling with adaptive binning, no global sort or hand-tuned thresholds).
3. Across 13 memory-intensive workloads and against 7 state-of-the-art tiering systems, PACT runs up to 61 percent faster than the best of them while performing up to 50 times fewer migrations, and closely tracks the top baseline (average gap 4.1 percent) even when it is not first. The trade-offs: PAC is a modeled estimate (accurate but not ground truth), it depends on the right hardware counters and on phase stability holding, and it improves placement transparently rather than changing the application or hardware, so gains are bounded by how much better placement can help. This explainer is based on the paper's full text; the model and migration details should be confirmed in the paper, which is open-source.

Check yourself

Check your understanding

1. Why is access frequency (hotness) an unreliable way to decide which pages belong in fast memory?
2. What is Per-page Access Criticality (PAC), and how does PACT estimate it online?
3. What are PACT's two migration policies, and why are they shaped that way?
4. What does PACT achieve, and what are the limits of the approach?

Sources

The paper is “PACT: A Criticality-First Design for Tiered Memory” by Hamid Hadian, Jinshu Liu, Hanchen Xu, Hansen Idden, and Huaicheng Li (Virginia Tech), published at ASPLOS 2026, DOI 10.1145/3779212.3790198. The authors host a copy at people.cs.vt.edu, and PACT is open-source at github.com/MoatLab/PACT.

This explainer is written from the paper’s full text (the authors’ hosted copy). PACT is an online, page-granular tiered memory design that makes performance criticality a first-class principle via Per-page Access Criticality (PAC), a metric of each page’s contribution to CPU stall time. PACT estimates PAC online with a lightweight analytical model (from a 96-workload study) that predicts per-tier stalls from last-level-cache misses, latency, and memory-level parallelism, decomposing MLP per tier via hardware queue-occupancy counters and Little’s Law using only four standard counters, and leveraging phase stability for per-page attribution. It migrates pages with eager demotion and adaptive promotion to handle the skewed criticality distribution. Evaluated on 13 workloads against 7 state-of-the-art tiering systems, the paper reports up to 61 percent improvement over the best baseline and up to 50 times fewer migrations. Background on tiered memory, CXL, memory-level parallelism, and Little’s Law is standard context. The numbers are the paper’s own; exact mechanisms and full results should be confirmed in the paper.