iSwitch: QEC on Demand via In-Situ Encoding of Bare Qubits for Ion Trap Architectures

Keyi Yin, Xiang Fang, Zhuo Chen, David Hayes, Eneet Kaur, Reza Nejabati and 6 others

Protecting a quantum computer from errors with full error correction is so expensive it needs millions of physical qubits, out of reach for near-term machines; this paper (UC San Diego, Quantinuum, UCLA, Oak Ridge, and colleagues — Keyi Yin, Yufei Ding, and others) presents iSwitch, which notices that trapped-ion computers already do single-qubit operations almost perfectly, so it runs those on cheap unprotected "bare" qubits and only pays for error correction on the noisier two-qubit gates — switching qubits between bare and protected forms on demand to cut qubit and operation counts by a third to a half.

The argument in one glance

Problem

Making a quantum computer error-free the standard way needs millions of qubits

Quantum computers are held back by noise: every operation introduces a small error, and these errors accumulate across a circuit, so a program that leaves its qubits unprotected can only run a few operations deep before the result is garbage. Quantum error correction (QEC) is the accepted way out — it encodes the information of one reliable "logical" qubit across many noisy physical qubits, so that errors can be detected and corrected, allowing arbitrarily long computations in principle. But full fault-tolerant quantum computing, in which every single operation is performed in this protected way, is extraordinarily expensive, for two reasons. First, each logical qubit needs many physical qubits to encode it (a surface code, for instance, spends a large grid of physical qubits per logical qubit). Second, error-correcting codes can only perform certain gates directly; other essential gates — the non-Clifford gates, like the small rotation needed for general computation — are not native to the code, and the standard way to realize them, magic state distillation, consumes a large number of extra ancilla qubits and a lot of runtime. Put together, a fully fault-tolerant machine may require on the order of millions of physical qubits. Near-term devices have thousands. So the gold-standard approach to reliability is simply unavailable on the hardware people actually have, and will have soon.
What people did

Do early fault tolerance: apply some QEC, cheaply, with state injection

Because full fault tolerance is out of reach, researchers pursue "early fault-tolerant" (EFT) computing — apply some error correction, not all, to get useful results on the coming generation of machines (thousands of physical qubits, bigger than today's noisy devices but short of full fault tolerance). A leading EFT technique is state injection: instead of building expensive magic state distillation factories to make non-Clifford gates perfectly, it implements those gates at reduced fidelity, freeing resources for encoding the logical qubits. This deliberate trade of some accuracy for far less overhead lets EFT schemes boost the fidelity of near-term algorithms, and it targets applications with only sparse non-Clifford gates — like the variational algorithms VQE and QAOA that are promising for near-term quantum advantage.
Why it fell short

State injection still pays overhead and ignores what the hardware is good at

State injection helps but is still not efficient enough. It carries its own overhead: the ancilla logical qubit used during state preparation must itself be protected by QEC, and the injection circuit adds extra quantum operations and routing. More fundamentally, it is a general, hardware-agnostic method — it does not exploit the specific strengths of the machine it runs on, such as which gates a given platform performs unusually well, how its qubits are connected, or its particular noise profile. That is a missed opportunity, because near-term hardware has real, exploitable strengths. On a trapped-ion quantum computer, for example, single-qubit gates are already astonishingly accurate — around 99.9999 percent fidelity — good enough to meet early-fault-tolerant targets on their own, with no encoding at all; and the grid-based architecture these machines use, in which ions are physically shuttled between trap zones, lines up naturally with the two-dimensional layout of surface-code patches and makes two-qubit logical operations efficient. A method that ignores all this leaves easy wins on the table. What was missing was an error-correction strategy tailored to the hardware: one that spends protection only where the hardware is actually weak, and runs unprotected where the hardware is already good enough.
This paper's idea

Apply QEC only where needed, switching qubits between bare and protected on demand

iSwitch is a hybrid architecture for trapped-ion quantum computers that applies error correction selectively, in space and time, rather than to everything. Its guiding insight comes from the hardware: because trapped-ion single-qubit gates are already accurate enough for early fault tolerance, iSwitch runs single-qubit operations on bare (unencoded) qubits — including the non-Clifford gates that would otherwise demand magic state distillation or state injection — and reserves QEC-encoded logical qubits for the noisier two-qubit gates, whose logical form is made efficient by the machine's ion-shuttling grid. This selective encoding avoids full logical encoding, gate synthesis, and magic state distillation entirely. Making it work requires switching a qubit between its bare and logical forms on demand, in place, which iSwitch enables with three coordinated pieces. A runtime encoding protocol performs low-noise conversion between bare and logical qubits, letting rotation gates run without extra ancilla logical qubits. A hardware-aware hybrid instruction set partitions the machine into bare, logical, and interface regions and gives the compiler tailored instructions to coordinate operations and encoding transitions, hiding the details of individual physical qubits. And a compiler with dynamic encoding decides where and when to switch encodings, routes qubits, and schedules gates in a fidelity- and resource-aware way, minimizing the noisy code-switch operations. On variational quantum algorithm benchmarks, iSwitch reaches fidelity comparable to conventional QEC while using roughly 33 to 50 percent fewer qubits and operations — 50 percent fewer qubits than standard full fault tolerance and 33 percent fewer than prior EFT methods at the same budget — a practical, resource-efficient path to early fault-tolerant computing on trapped ions.

Why this problem is worth solving

Error correction is the gate to useful quantum computing, but its full cost is a decade away, so anything that delivers reliability sooner on real hardware is enormously valuable.

Quantum computing only becomes practically useful once noise is controlled, and error correction is the only known way to control it well enough for large problems. But the full version is astronomically expensive — millions of physical qubits — while the machines arriving in the next few years will have thousands. That gap means the field cannot simply wait for full fault tolerance; to get any practical value from near-term hardware, it must find ways to apply just enough error correction to matter, within the resources that exist. This is the entire premise of early fault tolerance, and its payoff is concrete: it is the difference between near-term quantum computers being scientifically interesting toys and being able to run a useful algorithm with a trustworthy answer. Because every physical qubit and every operation is precious on these devices, a scheme that reaches the same fidelity with a third to a half fewer of them is not a minor optimization — it directly determines what problems fit on the hardware at all. Making error correction affordable in the early-fault-tolerant regime is therefore one of the highest-leverage things one can do to pull useful quantum computing forward in time.

The key is that protection is not uniformly needed — and the hardware tells you where to spend it.

The deep move in iSwitch is to reject the assumption, baked into full fault tolerance, that every operation must be protected equally. In reality, the need for protection depends on how error-prone each operation is, and that depends on the hardware. On a trapped-ion machine the situation is lopsided: single-qubit gates are so accurate they already meet the fidelity bar with no encoding at all, while two-qubit gates are the weaker link. Spending precious QEC resources to protect single-qubit gates on such a machine is almost pure waste. The right strategy is therefore to encode selectively — bare qubits where the hardware is already good enough, logical qubits only where it is not — which is exactly what iSwitch does. This only works because the same hardware that makes single-qubit gates cheap also makes the encoded two-qubit gates efficient: the ion-shuttling grid maps onto surface-code patches, so bringing two logical patches together for a two-qubit gate is natural. The catch is that a qubit must be able to move between its bare and logical forms as the circuit demands, and doing that conversion without injecting too much noise, and scheduling it well, is the real engineering. So the insight is simple — protect only what needs protecting, guided by the hardware — but cashing it in requires the conversion protocol, the instruction set, and the compiler that make on-demand encoding practical.

What people did before, and where it broke

Full fault-tolerant quantum computing. Protect every operation with QEC, encoding all qubits and using magic state distillation for non-native gates. Where it broke. It may need on the order of millions of physical qubits, far beyond the thousands available on near-term devices.
Magic state distillation for non-Clifford gates. Build factories that produce high-fidelity resource states to realize gates the code cannot do directly. Where it broke. It consumes a large number of ancilla qubits and substantial runtime, a dominant part of the full-FT overhead.
State injection for early fault tolerance. Implement non-Clifford gates at reduced fidelity to skip distillation factories. Where it broke. It still needs QEC to protect the ancilla logical qubit during state preparation, plus extra operations and routing, and it is hardware-agnostic.
Treat all gates as equally in need of protection. Apply the same encoding regardless of which operations the hardware does well. Where it broke. On trapped ions, single-qubit gates are already accurate enough, so protecting them wastes scarce resources.
The gap. No scheme applied error correction selectively, guided by the hardware’s actual strengths, switching qubits between bare and logical forms only where and when protection is needed.

How iSwitch works

Selective error correction, switching between bare and logical qubits on demand

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The idea

Protect selectively, and let the hardware decide where. iSwitch’s founding move is to spend error correction only on the operations that need it — the noisy two-qubit gates — while running the already-accurate single-qubit gates unprotected, choosing this split from the platform’s real error profile. Co-designing the error-correction strategy together with the hardware it runs on, rather than applying a generic code uniformly, is the same approach the work on co-designing quantum error-correcting codes and modular chiplets covered elsewhere on this site takes, matching the protection scheme to the machine’s structure. iSwitch tailors the encoding to trapped ions, where the lopsided gate fidelities make selective protection especially powerful.

Make error correction practical on the near-term devices that actually exist. Rather than assume the full fault-tolerant machine of the future, iSwitch is built for the thousands-of-qubits regime of the coming generation, squeezing useful reliability out of limited hardware. Engineering error correction to be lightweight and usable on near-term quantum devices, instead of only on idealized large ones, is the same goal the work on a lightweight, low-latency decoder for near-term devices (Lilliput) covered elsewhere on this site pursues, making QEC fit the constraints of hardware available now. iSwitch does this by encoding selectively so the qubit and operation budget stays within reach.

Compile the quantum program to minimize the expensive overhead. iSwitch’s compiler decides where and when to switch encodings, routes qubits, and schedules gates to keep the costly, noisy code-switch operations to a minimum, targeting the sparse-non-Clifford structure of variational algorithms. Optimizing a quantum program at the compiler level to reduce its dominant overhead, exploiting the structure of the target algorithms, is the same principle the work on a block-wise compiler optimization framework for quantum programs (Paulihedral) covered elsewhere on this site is built on, restructuring the circuit to cut cost. iSwitch’s dynamic-encoding compiler is what turns the selective-QEC idea into an efficiently scheduled circuit.

Following a rotation gate through iSwitch

Running a variational circuit with selective, on-demand encoding

A trace, drawn from the paper, of how iSwitch handles single- and two-qubit gates with selective QEC.

Step 1 of 5

A single-qubit rotation arrives

The circuit needs a non-Clifford single-qubit rotation on a qubit. On full fault tolerance this would demand magic state distillation or state injection; iSwitch instead runs it directly on a bare, unencoded qubit.

Trapped-ion single-qubit fidelity (about 99.9999 percent) already meets the target.

Why it works

Not every gate needs protection, so most encoding is waste. Full fault tolerance protects all operations equally → but on trapped ions single-qubit gates already meet the fidelity target unencoded → so running them on bare qubits removes protection that was never needed.
Selective encoding avoids the biggest overheads. Non-Clifford gates normally force magic state distillation or state injection → but running them on bare qubits sidesteps distillation, gate synthesis, and injection entirely → so the dominant sources of full-FT overhead disappear.
The same hardware makes the protected part efficient. Encoding only for two-qubit gates could be costly → but the ion-shuttling grid aligns with surface-code patches and brings them together → so logical two-qubit gates are efficient on exactly this platform.
In-situ conversion lets protection be applied on demand. Selective encoding needs qubits to move between bare and logical forms → but a low-noise runtime conversion protocol switches them in place → so a qubit is protected only during the operations that require it.
The compiler keeps the switching cost down. Code-switch operations are themselves noisy and could erode the savings → but a fidelity- and resource-aware compiler minimizes and schedules them → so the net result matches conventional QEC fidelity with far fewer resources.

What it costs (trade-offs and scope)

It is tailored to trapped ions, not universal. iSwitch’s advantage rests on trapped-ion strengths — ultra-high single-qubit fidelity and the shuttling QCCD grid; platforms without those characteristics would not see the same benefit, so this is a hardware-specific strategy, not a general QEC method.
Code-switching adds its own noise. Converting between bare and logical forms is not free of error, so the runtime protocol must be low-noise and the compiler must minimize switches; a workload that forced constant conversions would erode the gains.
It targets sparse-non-Clifford algorithms. The approach fits circuits like VQE and QAOA whose non-Clifford single-qubit rotations are sparse; a circuit dense in operations that do need protection would leave less room for the selective, bare-qubit savings.
Bare qubits meet the bar only in the early-fault-tolerant regime. Running single-qubit gates unencoded relies on their fidelity being good enough for EFT targets; it is not the full fault tolerance needed for arbitrarily large, deep computations, so iSwitch is a near-term, intermediate strategy rather than the endgame.
Reported gains are benchmark- and budget-dependent. The comparable fidelity and 33-to-50-percent resource reductions come from variational-algorithm benchmarks under specific comparisons (against full FTQC and prior EFT methods); the exact numbers depend on the algorithm, the hardware assumptions, and the resource budget.

The evaluation

Applying error correction on near-term trapped-ion computers

Property	Full fault tolerance	State injection (prior EFT)	iSwitch
What is protected
Non-Clifford gates
Uses hardware-specific strengths
Physical qubits needed
Fidelity

A comparison of error-correction strategies for near-term trapped-ion computers. By running high-fidelity single-qubit gates on bare qubits and encoding only for two-qubit gates, converting between bare and logical forms in situ, and scheduling the switches with a resource-aware compiler, iSwitch reaches fidelity comparable to conventional QEC while using roughly 33 to 50 percent fewer qubits and operations (50 percent fewer than full fault tolerance, 33 percent fewer than prior early-fault-tolerant methods) on variational algorithm benchmarks. Exact figures should be read from the paper.Underlined values explain themselves when clicked.

Where this stops working

What to keep in mind

This explainer is based on the paper’s full text (the authors’ arXiv copy, 2504.16303, of the ASPLOS 2026 paper). The described system is the paper’s: iSwitch is a hybrid architecture for trapped-ion quantum computers that applies quantum error correction selectively in space and time to enable early fault-tolerant (EFT) computing. It runs single-qubit operations (including non-Clifford rotations) on bare, unencoded qubits — exploiting trapped-ion single-qubit gate fidelity of about 99.9999 percent, which already meets EFT targets — and encodes qubits into logical form only for two-qubit gates, whose logical implementation is made efficient by the QCCD ion-shuttling grid’s alignment with two-dimensional surface-code patches. This avoids full logical encoding, gate synthesis, and magic state distillation. It has three modules: a runtime encoding protocol for low-noise in-situ conversion between bare and logical qubits (enabling rotation gates without extra ancilla logical qubits); a hardware-aware hybrid instruction set that partitions the machine into bare, logical, and interface regions; and a compiler with dynamic encoding that manages encoding switches, routing, and scheduling in a fidelity- and resource-aware way. The paper reports iSwitch achieves fidelity comparable to conventional QEC while reducing qubit and operation counts by roughly 33 to 50 percent (the paper states 50 percent fewer qubits than standard FTQC and 33 percent fewer than previous EFT methods under the same qubit budget, and up to a 43 times performance improvement over NISQ execution across EFT applications), evaluated on variational quantum algorithm benchmarks such as VQE and QAOA. The quantum-computing background above (QEC, magic state distillation, Clifford versus non-Clifford gates, surface codes, trapped ions) is standard context provided to make the approach intuitive. The step-by-step walkthrough is an illustration of the described mechanism. Exact protocols, the ISA and compiler details, and the full evaluation should be read from the paper.

Background

Why near-term quantum computing is a story of spending scarce protection wisely

It helps to see iSwitch within a broad pattern: quantum computing’s central near-term problem is that the perfect answer — full fault tolerance — costs far more than any real machine can afford, so progress comes from finding where you can safely spend less. Error correction is the only path to reliable quantum computation, but it is also the single largest consumer of qubits and operations, and the qubits are the scarcest resource there is. This forces a way of thinking that recurs across the field: rather than protect everything to the same lavish standard, identify what actually needs protecting and concentrate the effort there, exploiting whatever the hardware happens to do well for free. iSwitch is a sharp instance — it notices that a trapped-ion machine already does half the job (single-qubit gates) essentially perfectly, and refuses to pay to protect it, spending its budget only on the two-qubit gates that are genuinely weak. This is the same resource-conscious mindset that runs through the effort to build practical quantum systems within tight hardware limits, the terrain the work on a high-bandwidth shared quantum random-access memory architecture (fat-tree QRAM) covered elsewhere on this site occupies, engineering quantum architecture to make scarce resources go further. iSwitch’s contribution is to show that, by matching the error-correction strategy to the hardware’s real strengths and switching qubits between protected and unprotected forms only as the circuit demands, near-term trapped-ion machines can reach the fidelity of conventional error correction at a third to a half the resource cost.

If you remember only three things

1. Quantum computers are limited by noise, and quantum error correction (QEC) — encoding one reliable logical qubit across many physical qubits — is the accepted path to fixing it, but full fault tolerance is enormously expensive: many physical qubits per logical qubit, plus magic state distillation for non-native (non-Clifford) gates, potentially requiring millions of physical qubits when near-term machines have thousands. Early fault-tolerant (EFT) methods apply some QEC to get value sooner, and state injection is a leading one, but it still carries overhead (protecting ancilla logical qubits, extra operations and routing) and is hardware-agnostic, ignoring what a given platform does well.
2. iSwitch is a hybrid architecture for trapped-ion computers that applies QEC selectively, guided by the hardware. Because trapped-ion single-qubit gates are already about 99.9999 percent accurate — meeting EFT targets with no encoding — iSwitch runs single-qubit operations (including non-Clifford rotations) on bare, unencoded qubits, avoiding magic state distillation and state injection, and encodes qubits into logical form only for the noisier two-qubit gates, whose logical version is made efficient by the ion-shuttling QCCD grid aligning with surface-code patches. It switches qubits between bare and logical forms on demand via a low-noise runtime encoding protocol, a hybrid instruction set that partitions the machine into bare, logical, and interface regions, and a compiler that schedules the encoding switches in a fidelity- and resource-aware way.
3. On variational quantum algorithm benchmarks (VQE, QAOA), the paper reports iSwitch achieves fidelity comparable to conventional QEC while using roughly 33 to 50 percent fewer qubits and operations — 50 percent fewer qubits than standard full fault tolerance and 33 percent fewer than prior EFT methods at the same budget — and up to a 43 times performance improvement over unprotected near-term (NISQ) execution. The trade-offs: it is tailored to trapped ions (not universal), code-switching adds some noise so it must be minimized, it targets sparse-non-Clifford algorithms, and running single-qubit gates unencoded only suffices in the early-fault-tolerant regime rather than for arbitrarily deep computation. The reported numbers are benchmark- and budget-dependent.

Check yourself

Check your understanding

1. Why is full fault-tolerant quantum computing impractical on near-term hardware?
2. What is the central insight behind iSwitch's selective error correction?
3. What three pieces does iSwitch need to make on-demand switching between bare and logical qubits work?
4. What does iSwitch achieve, and what are the main limits on where it applies?

Sources

The paper is “iSwitch: QEC on Demand via In-Situ Encoding of Bare Qubits for Ion Trap Architectures” by Keyi Yin, Xiang Fang, Zhuo Chen, David Hayes, Eneet Kaur, Reza Nejabati, Hartmut Haeffner, Wes Campbell, Eric Hudson, Jens Palsberg, Travis Humble, and Yufei Ding (University of California San Diego; Quantinuum; Cisco Quantum Lab; University of California Berkeley; University of California Los Angeles; and Oak Ridge National Laboratory), published at ASPLOS 2026, DOI 10.1145/3779212.3790177. It is available on arXiv as 2504.16303.

This explainer is written from the paper’s full text (the authors’ arXiv copy). iSwitch is a hybrid architecture for trapped-ion quantum computers that applies quantum error correction selectively in space and time for early fault-tolerant computing. It runs single-qubit operations (including non-Clifford rotations) on bare, unencoded qubits — exploiting trapped-ion single-qubit fidelity of about 99.9999 percent — and encodes qubits into logical form only for two-qubit gates, whose logical implementation is made efficient by the QCCD ion-shuttling grid aligning with two-dimensional surface-code patches, avoiding full logical encoding, gate synthesis, and magic state distillation. It comprises a runtime encoding protocol for low-noise in-situ conversion between bare and logical qubits, a hardware-aware hybrid instruction set partitioning the machine into bare, logical, and interface regions, and a compiler with dynamic encoding for fidelity- and resource-aware switching, routing, and scheduling. The paper reports comparable fidelity to conventional QEC while reducing qubit and operation counts by roughly 33 to 50 percent (50 percent fewer qubits than standard FTQC, 33 percent fewer than prior EFT methods, and up to 43 times over NISQ execution) on variational algorithm benchmarks. Numbers are the paper’s own; exact mechanisms and full results should be confirmed in the paper.