HetEC: Architectures for Heterogeneous Quantum Error Correction Codes

Samuel A. Stein, Shifan Xu, Andrew W. Cross, Theodore J. Yoder, Ali Javadi-Abhari, Chenxu Liu and 6 others

The leading error-correcting code for quantum computers, the surface code, can run any algorithm but spends physical qubits at a rate that grows with the square of how many errors it must survive — while a newer family of codes packs far more logical qubits into the same hardware but cannot, on its own, run everything; HetEC (Pacific Northwest, Yale, IBM Quantum, Princeton, UC San Diego, Washington) builds one machine out of both, treating the dense code as memory and the surface code as a processor with a bus between them, and reports the first end-to-end accounting of what that split costs in qubits, time and errors.

The argument in one glance

Problem

Protecting a quantum computer costs more qubits than anyone can build

Physical qubits are noisy, so a usable logical qubit is spread across many of them and checked continuously. The surface code, the design everyone plans around, uses a square grid — surviving more errors means a wider grid, and the qubit count grows with the square of that width. Serious algorithms end up needing more than a million physical qubits.
What people did

Switch to a denser code

A family called quantum low-density parity-check codes packs many logical qubits into one block instead of one. The gross code, a recent example from IBM, holds 12 logical qubits in 144 physical ones at a comparable error threshold — a net rate of one logical qubit per 24 physical qubits, against hundreds for the surface code.
Why it fell short

The dense code cannot run a whole algorithm

It can store qubits and perform the cheap half of the gate set. The expensive half needs magic states, and every mature recipe for producing those is built on the surface code. How long the cheap gates take on the dense code in practice was also an open question. So it is a good memory and not yet a computer.
This paper's idea

Build one machine from both codes and measure what the seam costs

Make the surface code the processor and the dense code the memory, connect them with a 103-qubit ancilla bus, and load qubits across it when an expensive gate needs them. Then do the part nobody had done — compile real algorithms onto that machine and account for the qubits, the clock cycles and the errors.

Why this problem is worth solving

The cost that motivates everything here is a squaring.

A quantum error-correcting code laid out on a two-dimensional grid, where every check involves only neighbouring qubits — which is why it suits real hardware. Its parameters are one logical qubit encoded in d times d physical qubits, where d is the code distance, the smallest number of physical errors that can corrupt the logical qubit unnoticed. Its threshold is about 0.7 percent, meaning physical error rates below that get suppressed rather than amplified. Because the qubit cost grows as the square of the distance, buying more protection is expensive, and buying it for a thousand logical qubits at once is what pushes designs past a million physical qubits.

is not inefficient by accident; the locality that makes it buildable is also what makes it sparse.

The alternative is dense but incomplete.

A quantum low-density parity-check code from the bivariate bicycle family, encoding 12 logical qubits into 144 physical qubits at distance 12, with a threshold of 0.65 percent. Its logical qubits can be permuted inside the block by fault-tolerant operations called automorphisms, using only the connectivity the code already has. Sacrificing one of the 12 logical qubits to act as a port leaves the full cheap gate set available on the other 11. What it does not have is a route to the expensive gates that make computation universal.

is roughly an order of magnitude denser, which is precisely why it is worth the trouble of pairing it with something that can compute.

What people did before, and where it broke

Build the entire machine from surface code patches. The default plan, and the one with the most mature compilation story — decompose to a simple gate set, rewrite as Pauli rotations, and prune every cheap gate away. Where it broke. The qubit bill. In this paper’s own accounting, an 18-qubit adder takes 8,243 physical qubits and a 98-qubit Ising simulation takes 45,420, and those are before magic state factories are counted.
Move the whole machine to a dense code. If one code gives 12 logical qubits per 144 physical, use it for everything. Where it broke. Universality. The cheap gates can be done through surgery, but the time cost was unclear, and the expensive gates need magic states whose preparation protocols are all surface-code constructions. It is not a one-code solution.
Concatenate or nest the codes. Put a surface code underneath a dense code, or stack codes hierarchically, and characterise the resulting threshold. Where it broke. These are code-level results about error suppression. They do not say how an algorithm gets compiled onto the result, or what running one actually costs.
Quantum memory hierarchies. The idea that a quantum machine should have a memory region and a compute region is nearly twenty years old. Where it broke. It predates high-rate codes, so it was framed around codes of differing thresholds rather than codes of differing density, which changes what the hierarchy is buying.
Build the plumbing. Recent work supplies exactly the parts a two-code machine needs — ancilla systems that shrink from growing with the square of the distance to growing about linearly, a 103-qubit bus that gives the dense code its cheap gate set, adapters that connect a bus to a surface code at no extra qubit cost. Where it broke. Nothing broke. These are mechanisms, offered without an answer to whether assembling them into a computer is worth doing.
The gap. Nobody had compiled a real algorithm onto a two-code machine and added up the bill. The interesting questions only appear at that scale — what the traffic between codes costs, what happens to a compiler when the processor is too small to hold every operation, and how you schedule two codes whose clocks do not tick at the same rate.

How an algorithm reaches a two-code machine

Compiling to a processor made of one code and a memory made of another

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Three benchmark circuits from a public suite — a quantum adder, a single-layer Ising model simulation and a quantum Fourier transform — at sizes from 18 to 98 logical qubits.

The idea

A quantum computer with a memory hierarchy, where the hierarchy is made of codes. The move is the von Neumann split applied one level down than usual. Instead of separating processor from memory by what the hardware does, separate them by which error-correcting code the qubits are encoded in — a processor region of surface code patches that can perform every gate, a memory region of dense code blocks that stores qubits cheaply and performs the cheap ones, and a bus between them. The accounting changes character immediately: the qubits sitting idle during a long algorithm, which in a single-code machine each cost a full surface code patch, now cost a twenty-fourth of one. Splitting a quantum machine into regions and then discovering that the links between them dominate the design is a pattern the multi-fridge distributed machine covered elsewhere on this site ran into from the opposite direction, where the regions were separated by refrigeration rather than by encoding.

One door into memory, and a shift register behind it. The obvious way to connect the memory block to the bus is to give every logical qubit in it an attachment point. The paper prices that at over 1,200 physical qubits for a block that only contains 144, plus the physical headache of logical operators overlapping. So they attach exactly one — a probe qubit — and reach the other eleven by permuting the block. The permutation is an automorphism, a fault-tolerant reshuffle that uses only wires the code already has, and it turns out to cost about two permutations in each basis on average regardless of which qubit is wanted, which is what makes a single port tolerable rather than a bottleneck. Deciding how many entry points a shared communication resource should have, and paying qubits for each one, is the same question the multi-entry chiplet highway covered elsewhere on this site answers in the other direction, by building many doors on purpose.

The architecture reaches back into the compiler and takes something away. This is the finding that makes the paper an architecture paper rather than a codes paper. In a single-code machine, the compiler’s best trick is that every cheap gate can be pushed to the end of the circuit and absorbed for free. That trick relies on being allowed to grow the expensive gates without limit as it pushes. Give the processor a finite number of patches and the trick stops working partway through — cheap gates get stranded in the middle of the circuit, and now they must be executed rather than deleted. The recovery is that the memory code happens to support exactly those gates, so a limitation created by the split is absorbed by the other half of the split. Discovering that a hardware constraint has to be answered inside the code and the compiler rather than around them is the same lesson the work on co-designing error-correcting codes with defective chiplets covered elsewhere on this site arrives at from the manufacturing side.

Moving one qubit from memory into the processor

What it takes to run one expensive gate on a qubit that lives in memory

The compiler has produced a gate that acts on qubits which are not all in the processor region. Everything below happens for a single one of them.

Step 1 of 5

The gate cannot run where the qubit is

Expensive gates require every qubit involved to sit in the surface code region, because that is the only region with a route to magic states. If any of them is in memory, the gate waits.

This is why the schedule is built around movement rather than around gates. Operations whose qubits already sit entirely in one region get priority precisely because they need none of this.

Why it works

The idle majority is what a dense memory is for. In a real algorithm most logical qubits are waiting at any given moment → in a single-code machine each of those waiting qubits still occupies a full surface code patch sized for the whole algorithm’s error budget → moving them into a code that stores 12 for the price of one is where almost all of the qubit saving comes from.
The two codes fail in different places, and the split puts each one where it is strong. The surface code is sparse but universal → the dense code is efficient but cannot make magic states → assigning computation to the first and storage to the second means neither code is asked to do the thing it is bad at.
Losing the compiler’s best optimisation turns out to be survivable. Constraining commutation strands cheap gates in the middle of the circuit → but the memory code supports the full cheap gate set in place → and measurement shows only about 2 to 3 percent of gates end up executing in memory for these benchmarks, so the stranded gates are a minority rather than the common case.
One port is affordable because the permutation is nearly free. Attaching all 12 logical qubits to the bus would cost over 1,200 physical qubits → attaching one costs nothing extra and requires permuting the block instead → and the permutation is one clock cycle at an error rate hundreds of times below every other instruction, so paying about four of them per transfer barely registers.
The right question is not which code has the lower error rate. Both architectures land within the same order of magnitude on logical error for these circuits → but reaching a target error rate with pure surface code means raising the distance, and error falls exponentially in distance while qubits grow quadratically → so the surface code cannot shed much distance before its error explodes, which is why the qubit gap at equal error is as wide as 6.42 times.

What it costs (trade-offs and scope)

Time. Heterogeneous execution is slower on every benchmark. The headline is up to 3.43 times more logical clock cycles, and the average across the study is 2.53 times. That is the price of a bus.
Errors, usually. The logical error rate rises by an average factor of 1.99. There is one exception worth noting honestly — the 18-qubit Fourier transform actually comes out slightly better heterogeneously, at 0.83 times the single-code error rate, because in that circuit small processors keep the expensive gates narrow.
Nothing here has been built. The memory code, the bus and the magic state assumptions all come from other recent papers, several of them preprints. This is an architectural study assembled from published components, not a measurement of hardware.
The error model is an estimator, and the authors say so. Each instruction’s logical error rate is simulated in isolation, then substituted into the circuit and summed. The paper states plainly that it could be improved by a full error model capturing the dynamics of the heterogeneous system, and that assuming no ancilla routing overhead in the surface code makes the reported figure a lower bound.
The low-noise results rest on fitted numbers. Error rates at physical rates of one in ten thousand and one in a hundred thousand are interpolated rather than simulated, because the dense code’s behaviour there has not been studied much. That is exactly the regime where the paper finds movement errors dominating, so the most interesting conclusion sits on the least solid data — which the authors flag rather than bury.
The in-memory timing assumes the convenient qubits. Only four logical qubits support the cheap single-qubit rotations natively and three pairs support the two-qubit ones; everything else must be synthesised from about eight native rotations. The paper assumes those specific qubits get used, calls the general routing problem complex, and leaves it to future work.
Magic state factories are excluded from every qubit count. They are held constant across architectures, and the error contributed by magic states is assumed negligible on the strength of a recent low-overhead preparation scheme.
One logical qubit in each memory block is spent on being the port, leaving 11 of 12 usable.
Three benchmarks, all small. An adder, a single-layer Ising simulation and a Fourier transform, at 18 to 98 logical qubits. The generalisation to other code pairs is argued structurally rather than evaluated, and the paper notes that blocks with different permutation structures may need custom handling.

The evaluation

Running the same algorithm to the same target error rate

Property	All surface code	Surface code plus dense memory	What the numbers hide
Physical qubits
Logical clock cycles
Logical error rate	Baseline at a physical error rate of one in a thousand
Where the errors come from	Gates only
Tuning the processor width	Not a parameter

Three circuits from a public benchmark suite at 18 to 98 logical qubits, compiled through the authors' transpiler and scored with a per-instruction error estimator.Underlined values explain themselves when clicked.

Where this stops working

What to keep in mind

This is a design study, not a demonstration. No two-code machine exists; the dense memory code, the 103-qubit bus and the magic state assumptions are each taken from other recent papers, several still preprints. The error numbers come from an estimator that simulates each instruction’s logical error rate in isolation and then sums them over the compiled circuit, which the authors describe as improvable by a full error model and as a lower bound given that surface code ancilla routing overhead is assumed away. The results at physical error rates of one in ten thousand and one in a hundred thousand are fitted rather than simulated, and that is precisely the regime in which the paper finds movement errors dominating — the strongest conclusion resting on the weakest data, which the paper says out loud. The in-memory gate timing assumes the compiler can always use the four logical qubits and three pairs that support cheap rotations natively, with the general routing problem left to future work; the mitigating measurement is that only about 2 to 3 percent of gates run in memory for these circuits. Three benchmarks, all under 100 logical qubits, one of them a single layer. And the claim that the approach generalises to other code combinations is argued from structure rather than evaluated.

Background

Why error correction dominates every quantum architecture paper

It helps to know how much machinery is running underneath before any of this makes sense. A quantum computer does not correct errors occasionally; it corrects them continuously, measuring a full round of parity checks, decoding the result to work out where the errors were, and doing it again, forever, interleaved with the actual computation. That loop is why a logical qubit costs hundreds of physical ones, and it is also why the decoder has a hard real-time deadline — a decoder that falls behind generates a backlog that grows without bound, which is the constraint the real-time matching work covered elsewhere on this site exists to fight. Every number in this paper sits on top of that loop. A logical clock cycle is one round of syndrome measurement. An instruction’s cost is quoted in how many rounds it needs. The error rate of a gate is the probability the decoder guesses wrong. Once you see that, the appeal of a heterogeneous machine is easier to feel — a qubit sitting in memory still needs its checks measured and decoded every cycle, so putting twelve of them in the space of one is not just a storage saving but a reduction in how much of that perpetual machinery has to exist at all.

If you remember only three things

1. The surface code can run any quantum algorithm but spends physical qubits as the square of the protection it provides, while dense codes like the gross code store 12 logical qubits in 144 physical ones and yet have no mature route to the expensive gates that make computation universal — so the natural move is to build one machine from both, with the surface code as processor, the dense code as memory, and a 103-qubit bus between them.
2. Making that split work is mostly a compiler and scheduling problem rather than a physics one: a finite processor means cheap gates can no longer all be optimised away, so they get stranded and must instead execute in place in memory; only one logical qubit per memory block touches the bus, so fetching any other one means permuting the block first; and the two codes tick at different rates, so everything must be pinned to a common unit of one syndrome round.
3. Compiled end to end, the trade is roughly 7.81 times fewer physical qubits on average and up to 11.10 times, paid for with 2.53 times more clock cycles and about twice the logical error rate — but the error comparison is the wrong frame, because reaching a fixed target error rate with pure surface code means raising distance, which costs qubits quadratically while error falls exponentially, and that asymmetry is where the 6.42 times advantage at equal error actually comes from.

Check yourself

Check your understanding

1. Why pair two error-correcting codes instead of picking the better one?
2. What does the architecture take away from the compiler, and how is that recovered?
3. Why is only one logical qubit in the memory block connected to the bus?
4. The heterogeneous machine has a higher logical error rate on most benchmarks. Why is that not the decisive comparison?

Sources

The paper is “HetEC: Architectures for Heterogeneous Quantum Error Correction Codes” by Samuel Stein, Shifan Xu, Andrew W. Cross, Theodore J. Yoder, Ali Javadi-Abhari, Chenxu Liu, Kun Liu, Zeyuan Zhou, Charlie Guinn, Yufei Ding, Yongshan Ding and Ang Li, published at ASPLOS 2025, pages 515-528, DOI 10.1145/3676641.3716001.

This explainer is written from the full 14-page text. Everything above comes from the paper’s own sections: the background on code parameters, the surface code’s quadratic scaling and 0.7 percent threshold, the gross code as a 144-physical, 12-logical, distance-12 bivariate bicycle code with a 0.65 percent threshold supporting the Clifford group on 11 of its 12 logical qubits, and the ancilla bus history from constructions growing with the square of the distance to the 103-qubit monolayer system; section 3’s architecture, including the 1.5 times physical qubit assumption for surface code ancilla routing, the instruction tables with their clock speeds and simulated or fitted logical error rates, the pricing of full coupling at over 1,200 physical qubits, the two-stage automorphism-then-teleport movement protocol with its measured expectation of two permutations per basis, the modified commutation rule and the resulting persistence of Clifford gates, the 14-cycle native rotation figure with the caveat that other rotations need about eight native rotations and that general in-memory routing is left to future work, the measured 2 and 3 percent in-memory gate fractions, and the definition of a global logical clock as one measurement cycle; and section 5’s evaluation, covering the three QASMBench circuits, the error estimator and its stated status as a lower bound, the per-architecture table of physical qubits, error rates and clock cycles, the error breakdowns of 56.4 and 11.8 percent for the 28-qubit adder and 11.3, 14.8 and 73.9 percent for the 98-qubit Ising model, the average operator weights of 2.78 and 6.95 explaining the Fourier transform’s bell-shaped error curve, the observation that movement errors dominate at lower physical error rates where the numbers are interpolated, and the equal-target-error comparison yielding up to 6.42 times fewer physical qubits alongside the 32.6 percent qubit increase for a 175.8 percent speedup when widening the processor from 2 patches to 4.