Achieving Near-Zero Read Retry for 3D NAND Flash Memory

Flash memory does not store bits as ones and zeros but as trapped electric charge, and reading one back means asking whether the charge sits above or below a threshold voltage — a question that only works if you guess the threshold correctly, and the correct answer drifts as the chip ages and as the charge quietly leaks away; when the guess is wrong the drive simply tries again with a different threshold, working through a fixed list the manufacturer supplied, and on a worn chip that can take more than twenty attempts for a single read, cutting effective speed to a small fraction; this paper (Hong Kong and Xiamen) measures three commercial chips exhaustively and finds the manufacturer's list is close to arbitrary — it repeats guesses, bunches them together, and zigzags instead of advancing — while the real optimum turns out to sit on a straight line, so knowing one threshold gives you the others, and to move along it in step with the logarithm of how long the data has been sitting; rebuilding the list around that structure drops the average from over twenty retries to 0.003.

The argument in one glance

Problem

Reading old flash means guessing a threshold that has drifted

Flash memory does not store ones and zeros directly. Each cell holds an amount of trapped electric charge, and reading a bit means comparing that charge against a REFERENCE VOLTAGE to ask which side of the boundary it falls on. That works only while the boundary is in the right place, and it does not stay there. Repeatedly erasing and rewriting wears the cells so their charge distributions spread out, and stored charge slowly leaks away, so a boundary that once cleanly separated two stored values gradually stops separating them. When error correction can no longer repair the resulting mistakes, the drive performs a READ RETRY — reading the same data again with a different reference voltage. Each retry is another complete read, so the cost is direct and severe: on a heavily worn chip a single page can need more than twenty attempts, cutting effective read speed to a small fraction of nominal.
What people did

Work through a table of alternative voltages supplied by the manufacturer

Every flash chip ships with a READ RETRY TABLE built in — a list of alternative reference voltage settings to try, in order, when the first read fails. The controller starts at the first entry, and if error correction still cannot recover the data it moves to the second, and so on. This requires no measurement, no modelling and no state, works on any chip from that manufacturer, and is the mechanism every drive on the market uses today.
Why it fell short

The table wastes most of its attempts, in three separate ways

Measuring what those tables actually do reveals they are close to arbitrary. First, a single entry specifies all seven reference voltages at once, but each type of page needs only some of them — so from any one page's point of view many entries are literally IDENTICAL to earlier ones, and trying them is a guaranteed waste of a full read. Second, the entries that do differ are badly spaced, some bunched so close together that consecutive attempts learn almost nothing while gaps elsewhere go uncovered. Third, the order zigzags, moving away from the optimum and back again rather than advancing steadily toward it. The result is that a mechanism whose entire cost is measured in wasted reads spends most of its reads learning nothing, and the tables ignore the one thing that would fix this — that the drift they are chasing is not arbitrary but follows a predictable trend.
This paper's idea

Measure the chips, find the drift is structured, and rebuild the table around it

This paper (Hong Kong and Xiamen — Ye, Li, Lv, Zhang, Ren, Wen, Kuo, Xue) characterizes three commercial chips across thirteen wear levels and eight retention periods, and finds the drift is highly structured. The best reference voltages for a given page type lie on a STRAIGHT LINE, so knowing one determines the rest — collapsing a multi-dimensional search into a one-dimensional one. Their position moves in step with the LOGARITHM of how long the data has been stored, so the whole trajectory can be predicted rather than searched. And the window of voltages that still works shrinks predictably as the chip ages, which is precisely why retries multiply. They rebuild the table from those models, spacing entries so each new attempt covers half a fresh window, add a small static table of per-layer manufacturing deviations, and fine-tune using the error-correction syndrome as a cheap compass that indicates whether a guess is improving WITHOUT paying to decode. Average retries fall from over twenty to 0.003, with read latency within 2 to 5 percent of a chip that never retries at all.

Why this problem is worth solving

Storage that gets slower as it gets older is a familiar complaint, and this is one of the mechanisms behind it, so it is worth understanding precisely.

A flash memory cell stores data as an amount of electric charge trapped inside it, and the level of that charge determines the cell’s THRESHOLD VOLTAGE. In the common arrangement holding three bits per cell, the charge is programmed to one of eight distinguishable levels, and reading requires applying a series of seven REFERENCE VOLTAGES to work out which level a cell is in. Cells storing the same value do not all hold exactly the same charge, so each level is really a distribution, and a reference voltage works by sitting in the valley between two neighbouring distributions. Two effects move those distributions. Repeatedly erasing and rewriting a cell damages it, so its distribution widens. And trapped charge leaks away over time, so distributions drift downward the longer data sits unread — this RETENTION effect is the dominant source of errors. Once the distributions have moved enough that a reference voltage no longer sits in the valley, reads return wrong bits. Error correction fixes a limited number, and beyond that the drive performs a READ RETRY, reading again with different reference voltages. Since a retry is a complete additional read, total read time is simply the base time multiplied by one plus the number of retries — which is why a heavily worn chip needing more than twenty attempts runs at a small fraction of its rated speed

Everything therefore depends on how well the alternatives are chosen.

A READ RETRY TABLE is a list of alternative reference-voltage settings embedded in the chip by its manufacturer. Each ENTRY specifies an offset for every one of the seven reference voltages, the first entry is used for the initial read, and each subsequent entry is tried in turn until error correction succeeds. It requires no measurement or state and works across every chip of that model, which is why it is universal. Its weakness is that it is generic in two senses. It does not distinguish between the different PAGE TYPES stored in the same cells — since three bits per cell means three pages share one set of cells, and each page type needs only a subset of the seven voltages to be read, an entry that differs from an earlier one only in voltages this page does not use is, for this read, an exact repeat. And it is not derived from how the voltages actually drift, so its entries are spaced and ordered without reference to where the optimum is travelling. Because every wasted entry costs a complete read, these are not minor inefficiencies

What people did before, and where it broke

Work through the manufacturer’s table from the start. The standard behaviour. Simple and stateless, but on a worn chip it costs more than twenty reads per page, and much of that is spent on entries that are duplicates or are badly placed.
Remember where the last successful retry stopped. A natural improvement that starts the next read near where the previous one succeeded. It helps substantially, but it still inherits a table whose entries are poorly spaced and ordered, and still costs more than fifteen reads per page at heavy wear.
Estimate the right voltage from sample cells. Reserve some cells with known contents and read those to infer where the distributions have moved. This adapts to the actual chip, but costs storage on every page and still averages several retries at high wear.
Predict the voltage offline from a model. Build a model of drift and compute the offset rather than searching. Attractive, but a model fitted at one temperature transfers badly, and at heavy wear this approach fails to recover the data almost every time.
The gap. Every approach either accepts the manufacturer’s table as given or replaces it with a single prediction. Nobody had measured what the drift actually does in enough detail to discover that it is strongly structured, and then rebuilt the table so that each attempt is guaranteed to cover ground the previous one did not. That is the gap this paper fills.

How the retry sequence is rebuilt around measured structure

Characterize the drift, exploit its structure, then steer with a cheap signal

A generic table spends reads learning nothing

Manufacturer tables specify all seven reference voltages per entry although each page type uses only some, so many entries are exact repeats for a given read. The rest are unevenly spaced and ordered so the sequence zigzags rather than advancing, and every wasted entry costs a complete read.
↓ →
Measure what the drift actually does new

Three commercial chip types are characterized across thirteen wear levels from fresh to eight thousand cycles and eight retention periods from one hour to five years, using accelerated ageing at high temperature. Error rate as a function of reference voltage fits a smooth curve closely, with a well-defined minimum.
↓ →
Find that the best voltages lie on a line new

For a given page type, the optimal settings of its two relevant reference voltages fall on a straight line, whose slope barely changes with wear while its offset shifts predictably. So knowing one voltage determines the other, turning a search over several dimensions into a search along one.
↓ →
Find that they travel with the logarithm of time new

The optimal offsets move in proportion to the logarithm of how long data has been stored, and the window of voltages that still works shrinks the same way — which is exactly why retries multiply with age, since the target the table must hit is getting smaller.
↓ →
Rebuild the table so each attempt covers new ground new

Entries are generated from the models so that consecutive attempts overlap by half a working window, guaranteeing coverage with no gaps and no repeats, and ordered by increasing retention so the sequence advances steadily instead of zigzagging. Eight entries suffice.
↓ →
Fine-tune with the error-correction syndrome as a compass new

When the table alone does not succeed, the number of failed parity checks is used as a guide, since it tracks the underlying error count closely and can be read without paying to decode. The search nudges one voltage at a time in whichever direction lowers it, stopping when it rises, and remembers the answer for the rest of that block.

The idea

Characterize the device before designing around it. The manufacturer’s table is treated as a given by everyone, and the paper’s first contribution is simply to measure what it does and find it close to arbitrary — repeating entries that a given page cannot distinguish, bunching some attempts so tightly they learn nothing while leaving gaps elsewhere, and ordering them so the sequence moves away from the optimum and back again. That diagnosis is only possible because the authors first measured the underlying drift exhaustively across three chip types, thirteen wear levels and eight retention periods. Establishing empirically what a component actually does, rather than accepting the vendor’s configuration as the definition of the problem, is the same measure-the-real-device discipline covered elsewhere on this site, where careful characterization of production behaviour reveals that something everyone treats as arbitrary is in fact strongly patterned and therefore exploitable.

A correlation can collapse a search from many dimensions to one. The most valuable finding is geometric. Each page type needs two reference voltages set correctly, which sounds like a two-dimensional search, and with several voltages across page types the space grows quickly. But the measurements show the optimal settings lie on a straight line — the slope is essentially constant as the chip wears, and only the line’s position shifts. Knowing one voltage therefore determines the other, so the search is one-dimensional, and a table can be generated by walking along that line rather than covering an area. Discovering that the quantities you must jointly optimize are in fact tied together, so that one determines the rest, is a structural simplification the site rewards repeatedly — the counterpart of finding that two apparently separate resources are coupled, here used to shrink a search rather than to complicate a budget.

Steer with a signal that is cheap and honestly correlated. The fine-tuning step needs to know whether a candidate voltage is better or worse than the last one, and the direct way to find out is to attempt error correction, which is expensive. Instead the search uses the number of failed parity checks, which the authors verify tracks the actual error count closely, and which the hardware produces essentially for free. That turns a hill-climbing search into something affordable — nudge one voltage, see whether the count falls, continue while it does, stop when it rises. Using a cheap surrogate to guide a search is commonplace and often a trap, and the discipline that makes it work here is that the correlation was measured rather than assumed. It is worth contrasting with the case covered elsewhere on this site where a cache achieved an excellent hit rate that turned out not to affect performance at all — the same shape of reasoning, validated in one case and not in the other.

Reading a page from a worn chip

From twenty-three reads to essentially one

How a read proceeds under the rebuilt scheme. Numbers from the paper's measurements on commercial chips.

Step 1 of 5

What has gone wrong

The page was written long ago on a chip that has been erased and rewritten eight thousand times. Charge has leaked out of the cells, so the voltage distributions have drifted downward, and the reference voltage the drive would normally use no longer sits in the valley between them. The read returns too many wrong bits for error correction to fix.

retention is the dominant error source and grows steadily the longer data sits unread
the window of reference voltages that still works has also shrunk with wear, so the target is smaller than it was when the drive was new

Why it works

Each retry is a complete extra read → the cost of the scheme is exactly the number of attempts wasted → so eliminating entries that repeat or that land where the previous one already covered translates directly into speed.
One entry sets all seven reference voltages but each page type uses only some → entries differing only in unused voltages are exact repeats for that page → generating a separate sequence per page type removes those guaranteed wasted reads.
The optimal voltages for a page type lie on a straight line whose slope barely changes with wear → knowing one determines the others → so the table can be generated by walking a line rather than covering a plane.
Optimal offsets move with the logarithm of storage time and the working window shrinks the same way → both can be predicted rather than searched → letting entries be spaced to overlap by half a window, which guarantees coverage without redundancy.
The count of failed parity checks tracks the true error count closely and costs nothing to obtain → it can steer a hill-climbing search without attempting decoding → making fine-tuning affordable where direct evaluation would not be.

What it costs (trade-offs and scope)

It must be built per chip model, from real measurement. The models come from characterizing specific commercial parts across many wear and retention levels, so a manufacturer or drive vendor must run that campaign for each new chip. This is not a firmware change that transfers unchanged.
The results rest on accelerated ageing. Five years of retention is emulated by holding chips at high temperature, using a standard conversion. That is normal practice in the field, but it is an extrapolation rather than a five-year observation.
Extra state must be maintained. Beyond a small table there is a per-layer deviation table and per-block remembered offsets, which the paper puts at about 160 kilobytes for a one-terabyte drive — small, but real state that must be tracked, reset on erase and kept consistent.
One error mechanism is deliberately set aside. Disturbance from reading neighbouring cells is judged to require far too many occurrences to matter and is not modelled, so the scheme addresses wear and retention rather than every source of error.
The fine-tuning search assumes a well-behaved landscape. Nudging one voltage at a time and stopping when the parity-check count rises works because the error curve has a single clean minimum, which the measurements support for these chips but which is an assumption the method depends on.

The evaluation

Three latest-generation triple-level-cell chips from different manufacturers were characterized on a commercial test platform, using ten chips of each type and more than two hundred blocks per chip, across thirteen wear levels from fresh to eight thousand program-erase cycles and eight retention periods from one hour to five years emulated by accelerated ageing. The resulting scheme was compared against five alternatives — the manufacturer’s table used plainly, the same table with the last successful entry remembered, estimation from reserved sample cells, offline model prediction, and a pipelined retry optimization — on both synthetic and real production workload traces.

Recovering data from aged flash

Property	Manufacturer table	Table plus remembered position	Rebuilt from measurement
Distinguishes page types
Spacing of attempts
Order of attempts
Average retries at heavy wear
Read latency versus no retry

At eight thousand program-erase cycles the rebuilt scheme averages 0.003 retries against more than twenty for the manufacturer's table, and holds read latency within 2 to 5 percent of a chip that never retries. It also recovered every page tested using only fast error correction, where competing methods failed on 25 to 100 percent of reads at that wear level and would have to fall back to a much slower correction mode.Underlined values explain themselves when clicked.

Where this stops working

What to keep in mind

Read this as a result about specific measured devices. The models are fitted to three commercial chip types through an extensive characterization campaign, so applying the approach to a new chip means repeating that campaign — this is not a firmware change that transfers unchanged, and it is most naturally done by whoever manufactures the part or the drive. The retention behaviour is obtained by accelerated ageing at high temperature using a standard conversion rather than by observing chips for five years, which is normal practice but remains an extrapolation. The scheme also maintains real state: a small table, a per-layer deviation table, and remembered offsets per block, together around 160 kilobytes for a one-terabyte drive, which must be reset on erase and kept consistent. One error mechanism is deliberately excluded, since disturbance from reading neighbouring cells is judged to need far too many occurrences to matter, so this addresses wear and retention rather than every source of error. And the fine-tuning search assumes the error curve has a single clean minimum so that stopping when the parity-check count rises is safe — well supported by the measurements here, but an assumption the method rests on. Within that scope the lessons travel well beyond storage: measure what a component actually does before accepting its vendor configuration as the problem; look for correlations that collapse a multi-dimensional search into one dimension; space your attempts so each covers ground the last did not; and steer with a cheap signal only after verifying it really tracks the expensive one.

Background

Measure the device, find the structure, and make every attempt count

This paper sits in the site’s storage and systems cluster and rhymes with several ideas covered elsewhere on this site. Its foundation is the same look-for-structure-in-what-seems-arbitrary move the cloud-capacity page makes when it measures why machines are actually reclaimed and discovers the pattern behind it — here an exhaustive characterization shows that voltage drift, which vendor tables treat as something to be groped for, in fact travels along a straight line and moves with the logarithm of time, and is therefore predictable. Its most elegant consequence, that the optimal voltages are tied together so knowing one determines the rest, is the mirror image of the coupled-resources insight the network-aggregation page relies on: there two resources being linked complicated a budget, here two variables being linked collapses a search. Its redesign of the retry sequence so that consecutive attempts overlap by exactly half a working window is the same make-every-probe-informative discipline the concurrency-fuzzing page shows when it mutates at a level where every mutation necessarily produces new behaviour, and the compiler-testing page shows when it maximizes the diversity of the implementations it compares. And its use of the error-correction syndrome as a cheap compass is a validated version of the pattern the open-hardware page warns about, where a cache hit rate looked excellent while contributing nothing — the difference being that this correlation was measured before it was trusted, which is exactly the discipline that separates a useful surrogate from a misleading one.

If you remember only three things

1. Flash stores each bit as trapped electric charge, and reading it means comparing that charge against a reference voltage sitting in the valley between two charge distributions. Those distributions move — erasing and rewriting wears cells so their distributions widen, and charge leaks away over time so they drift, with retention the dominant error source. Once a reference no longer sits in the valley, reads return too many wrong bits, and the drive performs a READ RETRY with a different reference taken from a fixed table the manufacturer embedded. Every retry is a complete extra read, so on a heavily worn chip a page can need more than twenty attempts and effective speed collapses.
2. Measuring three commercial chips across thirteen wear levels and eight retention periods shows those tables waste most of their attempts in three ways. An entry sets all seven reference voltages although each page type uses only some, so many entries are exact repeats for a given read; the entries that do differ are bunched in places and leave gaps elsewhere; and the order zigzags rather than advancing. The same measurements reveal the drift is highly structured — the optimal voltages for a page type lie on a STRAIGHT LINE whose slope barely changes with wear, so knowing one determines the rest and a multi-dimensional search becomes one-dimensional, and they move with the LOGARITHM of storage time while the window that still works shrinks the same way, which is exactly why retries multiply with age.
3. Rebuilding the table from those models gives eight entries spaced to overlap by half a working window, ordered by increasing retention so the sequence advances monotonically, plus a small static table of per-layer manufacturing deviations and a fine-tuning search steered by the count of failed parity checks — a signal verified to track the true error count and obtainable without paying to decode. Average retries at eight thousand cycles fall from over twenty to 0.003, read latency stays within 2 to 5 percent of a chip that never retries, and every page tested was recovered using only fast error correction where competitors failed on 25 to 100 percent. The transferable lessons: characterize before designing; find correlations that collapse a search; and space attempts so each covers new ground.

Check yourself

Check your understanding

1. The manufacturer's table specifies all seven reference voltages in every entry. Predict why that alone wastes reads.
2. The measurements show the optimal reference voltages for a page type lie on a straight line. Predict why that matters so much.
3. The fine-tuning search uses the count of failed parity checks rather than attempting error correction. Predict why, and what makes it safe.
4. The rebuilt table spaces consecutive entries to overlap by exactly half a working window. Predict what that achieves.

Sources

Achieving Near-Zero Read Retry for 3D NAND Flash Memory (ACM DL, DOI 10.1145/3620665.3640372) — ASPLOS 2024, pages 55 to 70; full text read for this explainer.
dblp record — bibliographic entry and author list.