Temporal and SFQ pulse-streams encoding for area-efficient superconducting accelerators

Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Darren Lyles and George Michelogiannakis

Superconducting circuits switch at tens of gigahertz and use about a millionth of the energy of ordinary chips, which makes them a serious candidate for future computing — but they can only be manufactured with a few tens of thousands of switching devices per chip, and that is the whole problem, because a single 8-bit multiplier built the conventional way consumes 86 thousand of them, more than an entire chip can hold; this paper (Berkeley Lab) argues the waste is self-inflicted, since the technology's natural signal is a picosecond PULSE while designers have been treating pulses as if they were the voltage levels of ordinary logic, an assumption carried over from a completely different substrate; encode numbers the way pulses actually behave — how MANY arrive in a window, and WHEN one arrives within it — and multiplication becomes a single gate while addition becomes counting, shrinking that multiplier from 86 thousand devices to about 16; the honest catch is that this buys area with time, since the encoding takes exponentially longer as precision grows, so it wins decisively below about 10 bits and loses above.

The argument in one glance

Problem

One multiplier costs more devices than an entire superconducting chip holds

Superconducting logic is a serious candidate to succeed conventional chips. It switches at tens of gigahertz and uses roughly a MILLIONTH of the switching energy, which is why it keeps being investigated despite needing to be kept extremely cold. Its hard limit is manufacturing density — there is about a thousandfold gap between how many devices fit on a superconducting chip and on a conventional one, leaving only a few tens of thousands of switching elements per chip. That budget is impossible to work within today, because a single 8-bit multiplier built in one common style consumes 86 thousand devices, and 817 thousand in another. One arithmetic unit already exceeds an entire chip. Building a useful accelerator is therefore arithmetically impossible before anyone starts, and superconducting prototypes have stayed tiny as a result.
What people did

Build superconducting circuits the way conventional chips are built

The standard approach designs superconducting logic the way everyone knows how — binary numbers, gates combining them, arithmetic units assembled from those gates. This is entirely reasonable. It reuses decades of accumulated design knowledge, established tools, and well-understood arithmetic circuits, and it means a superconducting design can be reasoned about with exactly the same mental model as any other chip.
Why it fell short

That design style was inherited from a substrate that works differently

The trouble is that conventional logic represents a bit as a voltage LEVEL held steady on a wire, while superconducting logic represents information as a picosecond PULSE that appears and is gone. Building level-based binary arithmetic out of pulses means constantly storing and re-synchronizing them, which is why superconducting logic needs MORE devices for the same binary design than conventional technology does — the opposite of what a denser, faster technology should deliver. The mismatch compounds with precision, since a binary multiplier grows steeply with bit width, and it forces a global clock reaching every cell for synchronization. So the very design style that makes superconducting chips easy to reason about is what makes them impossible to fill usefully.
This paper's idea

Encode numbers the way pulses naturally behave, and arithmetic almost disappears

This paper (Berkeley Lab — Gonzalez-Guerrero, Bautista, Lyles, Michelogiannakis) argues the waste is self-inflicted and changes the representation instead of the circuits. Two encodings suit pulses natively. In RACE LOGIC a number is WHEN a pulse arrives — which time slot within a window. In PULSE-STREAM encoding a number is HOW MANY pulses arrive in a window, with every pulse carrying identical weight. Combine them, holding one operand as a stream and the other as a timing, and arithmetic collapses: multiplication becomes a single gate letting one signal through while the other permits it, and addition becomes counting pulses together. Their multiplier costs about 16 devices instead of 86 thousand, and stays constant no matter the precision, while a full multiply-accumulate unit costs 126. The honest cost is that this buys area with time, because the number of pulses needed grows exponentially with precision, so the approach wins decisively below about 10 bits and loses above — and it comes with a striking side effect, since when every pulse weighs the same, losing 30 percent of them degrades accuracy gracefully where binary would collapse.

Why this problem is worth solving

The appeal of this technology is real and so is the wall it has hit, so it is worth being precise about both.

SUPERCONDUCTING LOGIC computes using JOSEPHSON JUNCTIONS, each a sandwich of superconductor, insulator and superconductor. When the current through one exceeds a critical threshold it switches and emits a single voltage pulse only picoseconds wide. Circuits built this way — called SINGLE FLUX QUANTUM logic — switch at tens of gigahertz and consume around a millionth of the switching energy of conventional chips, which is why the technology remains a serious candidate despite requiring extreme cooling. What blocks it is manufacturing density. Roughly a thousand times fewer devices fit on a superconducting chip than a conventional one, so a design has a budget of a few tens of thousands of junctions in total. That makes junction count the currency in which every design decision is priced, and it is a brutal budget: an 8-bit multiplier built in the conventional binary style consumes 86 thousand junctions in one design and 817 thousand in another, so a single arithmetic unit does not fit on a chip at all

. Every prototype has therefore stayed small, and the technology has never been given a fair test at useful scale.

The reason the budget is spent so badly turns out to be a choice, not a law.

Conventional logic represents a number in BINARY, where each bit is a voltage level held steady on a wire and the bits carry exponentially different significance. That does not fit a technology whose signal is a fleeting pulse. Two alternatives do. In RACE LOGIC, also called temporal encoding, the value is WHEN a pulse arrives — divide a window into slots, and the slot the pulse lands in is the number. Comparing two values becomes trivial, since whichever pulse arrives first is smaller, but arithmetic is awkward. In PULSE-STREAM encoding, also called unary or rate encoding, the value is HOW MANY pulses arrive within the window, each carrying identical weight. This makes arithmetic remarkably natural: multiplication becomes filtering one stream through a gate controlled by another, and addition becomes merging two streams and counting. The crucial structural difference from binary is that no pulse is more important than any other, which changes both how much circuitry arithmetic needs and how the system behaves when signals are lost

What people did before, and where it broke

Bit-parallel binary superconducting designs. Lay out binary arithmetic much as a conventional chip would, with all bits processed together. Familiar and fast per operation, but an 8-bit multiplier costs 817 thousand junctions, which is more than an order of magnitude beyond a whole chip’s budget.
Wave-pipelined binary designs. A more efficient style where a computation flows through logic as it arrives rather than marching to a global clock, bringing the same 8-bit multiplier down to 86 thousand junctions. A large improvement that still exceeds an entire chip.
Global clocking of every cell. Conventional superconducting logic requires synchronizing pulses at each element, since a pulse must be captured and re-emitted rather than simply held as a level. That synchronization machinery is a large part of why binary designs cost more junctions here than in conventional technology.
Race logic alone. Temporal encoding is spectacularly good at some operations — computing a minimum costs 8 junctions against roughly four thousand in binary — but multiplication and addition in that representation are expensive, so it cannot carry a general arithmetic pipeline by itself.
The gap. Everyone was optimizing circuits while keeping the binary representation that caused the problem, and the one pulse-native alternative was strong only for the operations arithmetic does not mostly consist of. What nobody had done was combine representations so that each is used where it is cheap. That is the gap this paper fills.

How arithmetic almost vanishes when the encoding fits the signal

Hold one operand as a count of pulses and the other as a timing, then let gates do the work

Binary arithmetic overruns the whole chip

Superconducting chips allow only tens of thousands of junctions, yet an 8-bit binary multiplier costs 86 thousand in the efficient style and 817 thousand otherwise, because level-based binary logic must constantly capture and re-synchronize pulses that were never meant to be held still.
↓ →
Encode one operand as how many pulses arrive new

A value between zero and one becomes a train of pulses within a window, where the fraction of the maximum possible pulses is the number. Every pulse carries identical weight, so the representation has no notion of a more or less significant digit.
↓ →
Encode the other as when a pulse arrives new

The second operand uses race logic, where the window is divided into slots and the slot in which a single pulse arrives encodes the value. This costs almost nothing to represent and is naturally suited to gating a stream over part of a window.
↓ →
Multiply with one gate new

With one operand as a stream and the other as a timing, multiplication becomes letting the stream through only while the timing signal permits it, which a single non-destructive memory cell performs. The result is about 16 junctions, constant regardless of precision, against 86 thousand for the binary equivalent.
↓ →
Add by counting, carefully new

Merging two streams costs 5 junctions but loses pulses when two arrive simultaneously. The paper instead builds a balancer from flip-flops facing each other, which handles simultaneous arrivals by emitting one pulse to each output, and cascades these into counting networks — 11 to 200 times smaller than binary adders.
↓ →
Let pulses flow instead of clocking every cell new

Because the encoding carries meaning in the pulses themselves, computation starts as soon as operands arrive and advances as a wave through the logic, without a global clock synchronizing each element. Pulses must be spaced to avoid collisions, which is what sets the minimum timing.

Assembled into three accelerators — a multiply-accumulate processing element at 126 junctions, a dot-product unit, and a finite impulse response filter — and simulated against binary superconducting equivalents across precisions and sizes.

The idea

The representation, not the circuit, was the thing wrongly inherited. Years of effort went into making superconducting binary arithmetic smaller, and the gains were real — the wave-pipelined style is roughly ten times better than the bit-parallel one. But both keep an assumption imported from a different substrate, that a number should be a set of weighted bits held as steady levels. Superconducting logic does not hold levels; it emits fleeting pulses, and forcing them to imitate levels is what makes binary designs need MORE devices here than in conventional technology. Changing the representation rather than optimizing the circuit collapses a multiplier from 86 thousand junctions to 16. Recognising that the expensive thing is an assumption carried over from the substrate you came from, rather than anything about the problem, is the same re-derive-do-not-port discipline covered elsewhere on this site — in the graphics-processor page that borrows non-uniform memory from processors but rebuilds its policies because bandwidth rather than latency is what binds there, and in the firmware page whose whole method rests on what one instruction set happens to guarantee.

Choose an encoding that makes your operation trivial, then combine encodings. The reason arithmetic nearly disappears is that each operation is being expressed in a representation where it is almost free. If a number is how many pulses arrive, then multiplying by a fraction just means letting that fraction of them through, which is one gate; adding just means merging streams and counting. If a number is when a pulse arrives, comparison is simply which came first. Neither encoding is good at everything — race logic is superb at minimums and poor at multiplication — so the design holds one operand in each, using both where each is cheap. Selecting the representation so the work you need becomes a natural consequence of it, and keeping two representations rather than choosing, are moves covered elsewhere on this site in the page that makes the sparse vector a first-class hardware type so set operations become single instructions, and in the pages that keep two forms of the same data so each can be used where it wins.

Uniform weighting changes the failure mode, not just the area. The most interesting consequence was not the design target. In binary, bits carry exponentially different significance, so losing the top bit is catastrophic while losing the bottom one is nothing — errors are wildly unequal and the damage depends on which bit was hit. In a pulse stream every pulse carries the same weight, so losing pulses costs value in proportion to how many were lost, with no cliff. Measured on a filter, a 30 percent error rate destroys roughly 30 decibels of signal quality in the binary design but only about 4 in the pulse-stream one. The encoding chosen for area turns out to determine robustness too, which is the same degrade-gracefully-rather-than-fail property covered elsewhere on this site, where a system built to keep working through partial damage beats one that is correct until it suddenly is not.

Building a multiply-accumulate unit out of pulses

From 86 thousand junctions to 126

How the pulse-native encoding assembles into the basic unit of an accelerator. Numbers from the paper's simulations.

Step 1 of 5

The budget, and what binary spends

A superconducting chip allows a few tens of thousands of junctions in total. An 8-bit binary multiplier costs 86 thousand junctions in the efficient wave-pipelined style and 817 thousand laid out bit-parallel, so a single multiplier exceeds the entire chip and no accelerator is possible.

the cost grows steeply with precision, so higher accuracy makes the situation worse rather than merely more expensive
binary needs more junctions here than conventional technology needs transistors, because pulses must be captured and re-emitted rather than held as levels

Why it works

Superconducting logic emits fleeting pulses rather than holding steady levels → forcing binary arithmetic onto it requires constantly capturing and re-synchronizing those pulses → which is why binary designs need more devices here than in conventional technology, the opposite of what should happen.
A number encoded as how many pulses arrive makes multiplication a matter of letting a fraction through → one gate performs it → so the multiplier costs about 16 junctions instead of 86 thousand, and does not grow with precision.
The encoding carries meaning in the pulses themselves → computation can start when operands arrive and flow through the logic as a wave → removing the global clock synchronization that each cell would otherwise need.
Every pulse in a stream carries identical weight → losing pulses costs value in proportion rather than catastrophically → so a 30 percent error rate costs about 4 decibels of signal quality where binary loses about 30.
Representing a value as a count means the count doubles with each added bit → latency grows exponentially with precision while area stays flat → which is exactly why the approach wins below about 10 bits and loses above.

What it costs (trade-offs and scope)

Area is bought with time, exponentially. The number of pulses needed doubles with every extra bit of precision, so latency grows exponentially where binary grows linearly. This is the central trade and the authors state it plainly — the approach wins below roughly 10 bits and loses above.
It suits small accelerators, not large ones. For dot products the advantage holds below about 64 elements, is roughly neutral around 128, and reverses at 256 unless very low precision is acceptable. The savings come from fitting many small units in one chip, which stops helping once each unit is large.
Simultaneous pulses collide, and avoiding that costs latency. The naive merger loses pulses that arrive together, and the balancer that fixes this imposes a minimum spacing between pulses, so the timing floor is set by a hazard the representation itself creates.
Supporting machinery adds real overhead. Storing coefficients needs a circuit converting a slow clock into fast pulse trains, adding about 10 percent area, and storing race-logic values needs a delay buffer whose overhead is 2.5 times at 8 bits, improving to 1.3 times at 16.
Everything is simulated, and power has a caveat. Results come from circuit simulation rather than fabricated chips. Active power is minuscule, but the static power of resistive biasing dominates in this logic family — hundreds of microwatts against single-digit microwatts of active power — and removing it requires a different logic family costing 1.4 times the area.

The evaluation

The building blocks were simulated and assembled into three accelerators — a multiply-accumulate processing element used in spatial architectures, a dot-product unit of the kind at the heart of neural networks and signal processing, and a finite impulse response filter — then compared against binary superconducting equivalents in both bit-parallel and wave-pipelined styles across a range of precisions and sizes. Accuracy was assessed on a 16-tap filter driven by sinusoidal inputs, with error injected to test robustness, and junction counts, latency, throughput and power were reported throughout.

Building superconducting arithmetic

Property	Bit-parallel binary	Wave-pipelined binary	Pulse-stream and race logic
8-bit multiplier cost
Growth with precision
Clocking
Behaviour under errors
Where it wins

A complete multiply-accumulate element costs 126 junctions against 9 to 17 thousand for the binary equivalent at 8 bits, a 98 to 99 percent saving, and adders shrink by 11 to 200 times. At 32 taps and 8 bits a filter delivers about 40 thousand operations per junction against about 10 thousand for binary, but binary overtakes it above roughly 10 bits of precision, and above 128 elements the area advantage reverses.Underlined values explain themselves when clicked.

Where this stops working

What to keep in mind

Read the trade as the authors state it — area is bought with time, and exponentially. The number of pulses required doubles with every added bit, so latency grows exponentially with precision where binary grows linearly, which is why the approach wins decisively below about 10 bits and loses above. Its advantage also depends on size: for dot products it holds below roughly 64 elements, is neutral near 128 and reverses at 256, because the benefit comes from fitting many small units into a chip rather than from making any one unit fast. The representation creates its own hazard, since pulses arriving simultaneously collide and are lost, and the balancer that fixes this imposes a minimum spacing that sets the timing floor. Supporting machinery is not free either — converting a slow clock into fast pulse trains for coefficient storage costs about 10 percent area, and buffering race-logic values costs 2.5 times at 8 bits, improving to 1.3 times at 16. All results come from circuit simulation rather than fabricated hardware. And while active power is minuscule, this logic family is dominated by the static power of resistive biasing, hundreds of microwatts against single-digit microwatts of active consumption, which can be removed only by switching to a different family costing 1.4 times the area. Within that scope the lessons are general: check whether the expensive part of your design is an assumption inherited from a different substrate; choose a representation that makes your operation nearly free; and notice that the representation determines how the system fails, not only what it costs.

Background

The representation was inherited, and changing it changes both cost and failure

This paper sits in the site’s emerging-hardware and architecture cluster and rhymes with several ideas covered elsewhere on this site. Its central argument is that the expensive thing was never the circuits but the binary representation imported from a substrate that works differently — conventional logic holds steady voltage levels while superconducting logic emits fleeting pulses, and making pulses imitate levels is what makes binary designs cost more devices here than they would on the technology they came from. That is the re-derive-do-not-port lesson the non-uniform-bandwidth page teaches when it borrows an idea from processors but rebuilds its policies because a different resource is scarce, and the firmware-debloating page teaches when it builds a defence around what one particular instruction set happens to guarantee. Its method, choosing an encoding in which the needed operation becomes almost free and then holding two encodings so each is used where it is cheap, is the same reify-the-right-representation move the sparse-computation page makes when it promotes the sparse vector to a first-class hardware type so that set operations become single instructions, and the same keep-both-forms instinct that recurs whenever a system refuses to choose between two representations. Its honest area-versus-delay crossover near 10 bits is the same measured-threshold shape the kernel-machine-learning and cloud-capacity pages report, where the interesting answer is not which approach wins but where the boundary lies. And its finding that uniform pulse weighting yields graceful degradation — about 4 decibels lost against 30 for binary at the same error rate — is the degrade-do-not-collapse property the quantum-chiplet page pursues, arrived at here as a side effect of a decision made for area.

If you remember only three things

1. Superconducting logic switches at tens of gigahertz using roughly a millionth of the switching energy of conventional chips, but manufacturing allows only a few tens of thousands of switching devices — Josephson junctions — per chip. That budget is unusable with current designs, because a single 8-bit multiplier costs 86 thousand junctions in the efficient style and 817 thousand in another, so one arithmetic unit exceeds a whole chip. The reason is that these designs inherit binary arithmetic from conventional technology, which represents bits as steady voltage levels, while superconducting logic emits picosecond pulses — forcing pulses to imitate levels means constantly capturing and re-synchronizing them, which is why binary needs MORE devices here than on the technology it came from.
2. The fix changes the representation rather than the circuits, using two encodings native to pulses. In PULSE-STREAM encoding a number is how many pulses arrive in a window, every pulse weighing the same; in RACE LOGIC it is when a single pulse arrives within the window. Holding one operand in each, multiplication becomes letting the stream through while the timing permits, performed by one memory cell at about 16 junctions constant with precision, and addition becomes counting merged streams using a balancer that avoids losing simultaneous pulses. A full multiply-accumulate element costs 126 junctions against 9 to 17 thousand for binary at 8 bits, and computation flows as a wave without clocking every cell.
3. The honest cost is that area is bought with time exponentially, since the pulse count doubles per added bit, so the approach wins below roughly 10 bits and loses above, and its size advantage reverses beyond about 128 elements. But the representation also changes how the system fails: because every pulse carries equal weight rather than binary's exponentially different significance, a 30 percent error rate costs about 4 decibels of signal quality where binary loses about 30. The transferable lessons: check whether your expensive component is really an assumption inherited from another substrate; pick a representation that makes the operation you need nearly free; and remember the representation determines the failure mode as well as the cost.

Check yourself

Check your understanding

1. Superconducting logic is far faster and more efficient than conventional chips, yet binary designs need MORE devices on it. Predict why.
2. Encoding a number as a count of pulses makes multiplication cost one gate. Predict why, and what it costs in exchange.
3. At a 30 percent error rate the binary filter loses about 30 decibels of signal quality while the pulse-stream one loses about 4. Predict what causes the difference.
4. The paper reports that its approach wins below about 10 bits and loses above. Predict why stating that boundary matters more than a headline speedup.

Sources

Temporal and SFQ pulse-streams encoding for area-efficient superconducting accelerators (ACM DL, DOI 10.1145/3503222.3507765) — ASPLOS 2022; full text read for this explainer.
Open-access copy (UC eScholarship) — the openly archived version of the paper.
Artifact (Zenodo) — released simulation artifacts for the designs.