Superconducting qubits suffer an always-on ZZ interaction across every coupling — quintuple gate errors, 2–10× worse parallel execution, and correlated errors that break error correction — and the known fixes either redesign the chip (tunable couplers that add decoherence, exotic qubit mixes) or optimize pulses globally at exponential cost; this paper splits the problem so both halves stay tractable, optimizing each gate's pulses on tiny 4-qubit neighborhoods to also cancel the crosstalk on couplings BETWEEN driven and idle regions (composition covers any circuit, because every such coupling touches exactly one driven qubit), then scheduling with identity gates and layer splits — chosen by planar graph duality in polynomial time — to convert or eliminate the couplings pulses cannot reach — fidelity up 11× on average (81× peak) in simulation, and effective crosstalk on a real device cut from ~200 kHz to under 11 kHz.
The argument in one glance
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Problem
The noise that never turns off
Superconducting quantum chips connect qubits with couplings so that two-qubit gates are possible — and those couplings host a parasite: an always-on ZZ interaction that continuously entangles the phases of neighboring qubits whether or not any gate is running. Its rap sheet: roughly 5× higher two-qubit gate error rates, 2–10× further fidelity loss when gates run in parallel, and — worst for the long game — CORRELATED errors across multiple qubits, exactly the error class quantum error correction is weakest against.
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What people did
Redesign the chip, or optimize all the pulses at once
Hardware answers add machinery: tunable couplers that can be zeroed, heterogeneous qubit frequencies, multiple interfering coupling paths. Software answers exist in principle: since every gate is implemented by microwave pulses, treat the whole circuit as one big unitary and numerically optimize all pulses jointly to cancel crosstalk everywhere.
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Why it fell short
Hardware costs coherence; global software costs exponentials
Tunable couplers introduce new decoherence channels, shortening qubit lifetimes; heterogeneous and multi-path designs complicate fabrication and control — and none of these apply to the simplest devices (homogeneous fixed-frequency qubits, single untunable couplings, IBMQ-style) which happen to have the LONGEST coherence times. Global pulse optimization is cleaner in principle but its time and memory grow exponentially with qubit count: fine for toy circuits, hopeless beyond a handful of qubits.
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This paper's idea
Local pulses that cancel the border; scheduling that shapes the border
This Tsinghua + Tencent Quantum Lab collaboration splits suppression between two tractable layers. PULSES — each gate's pulses are optimized (on systems of at most ~4 qubits) to implement the gate AND cancel ZZ crosstalk on the CROSS-REGION couplings around it: couplings between driven and idle qubits. Composition covers arbitrary circuits, because every cross-region coupling touches exactly one driven qubit, whose pulse can own it. SCHEDULING — what pulses cannot reach (couplings wholly inside idle regions) is attacked by applying identity gates to chosen idle qubits (turning unreachable intra-region couplings into cancellable cross-region ones) and by splitting layers; choosing WHICH qubits, framed as a graph cut, dodges NP-complete max-cut via planar duality (cuts ↔ odd-vertex pairings in the dual graph), solved by matching and shortest paths in polynomial time. Results: 11× average (81× peak) fidelity gains on 4–12-qubit benchmarks, over 0.9 fidelity for most, compilation under 0.25 s — and on a real three-qubit device, effective ZZ strength drops from ~200 kHz to under 11 kHz.
Why this problem is worth solving
Most noise in quantum computing is event-driven — a gate fires
imperfectly, a measurement misreads.
an always-on interaction of the form
σz⊗σz between coupled qubits, arising from the interplay of
computational and higher energy levels. It continuously
rotates the phase of each qubit conditioned on its neighbor’s
state — during gates, between gates, and on completely idle
qubits — at strengths around 200 kHz on real devices. Because
it correlates errors across qubits rather than striking them
independently, it produces exactly the high-weight error
patterns that quantum error correction codes are provisioned
worst against
The hardware-versus-software tension frames the contribution.
Chip-level fixes work but tax the wrong budget: tunable
couplers trade crosstalk for decoherence, and the fixes
exclude precisely the simple homogeneous devices with the
best coherence times. The pure-software ideal — global
the layer beneath gates:
superconducting qubits are steered by shaped microwave
pulses, and a “gate” is just a pulse sequence driving the
system’s Hamiltonian so its evolution matches the intended
unitary. Pulse optimization tunes these shapes numerically —
and the same freedom that implements a gate can be spent
canceling unwanted Hamiltonian terms alongside it
What people did before, and where it broke
- Tunable couplers. Add a control knob per coupling to null the ZZ term. Effective — and each knob is a new decoherence channel, shortening qubit lifetimes; more fabrication and control complexity per pair.
- Heterogeneous qubits / multi-path couplings. Detune neighbor frequencies or engineer interfering paths so ZZ terms cancel by design. Both complicate fabrication, and neither retrofits the simplest fixed-coupling homogeneous devices — the ones with the longest coherence.
- Global pulse optimization. Optimize all pulses jointly against the whole-circuit unitary: exponential time and memory in qubit count. Correct on four qubits, unusable at twelve.
- Crosstalk-aware scheduling alone (gate-error flavor). Prior compiler work serializes gates whose SIMULTANEOUS execution interferes — but ZZ acts on idle qubits too, so scheduling without pulse cooperation leaves the always-on component untouched.
- The status-quo compiler default. Maximize parallelism (Qiskit-style ParSched) with standard Gaussian pulses — the baseline this paper beats by 11× average — implicitly optimizes for decoherence while ignoring crosstalk’s parallelism penalty.
How the co-optimization works
Pulses own the border; scheduling draws it
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Regions: the organizing picture new
In any layer (set of simultaneous gates), each qubit is either DRIVEN (a gate's pulses act on it) or IDLE. Connected components of same-status qubits form REGIONS; couplings then split into CROSS-REGION (driven-idle border) and INTRA-REGION (inside an idle or driven region). This classification decides everything: cross-region crosstalk is pulse-cancellable, intra-region is not.
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ZZ-suppressing pulse objectives, locally optimized new
Each gate's pulses are optimized with a dual objective: realize the gate unitary AND suppress the ZZ terms on the couplings bordering it. The scalability theorem: every cross-region coupling touches exactly ONE driven qubit, so the pulse of that qubit's gate can own its suppression — meaning optimization only ever runs on BASIC regions (a gate plus its bordering couplings, ≤4 qubits), and direct composition covers arbitrary layers. Exponential global optimization becomes a handful of small, cacheable problems.
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Pluggable pulse back-ends new
The framework accepts any pulse method that can meet the objective: quantum optimal control (OptCtrl), dynamically corrected gates, and a new perturbation-theory-based method (Pert) introduced here. Evaluation shows results are largely insensitive to the choice — the architecture, not the pulse engine, carries the win.
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Identity gates: actively doing nothing new
An idle qubit is NOT a safe qubit — its couplings to other idle qubits accumulate uncancelled crosstalk. Applying an IDENTITY gate (a pulse that implements "no operation") to a chosen idle qubit changes its status to driven: its couplings become cross-region, and the identity pulse cancels them. The scheduler picks which idle qubits get identities to minimize a weighted sum of N_C (couplings left unsuppressed) and N_Q (largest region size — a proxy for correlated-error weight).
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The cut formulation and planar duality new
Driven vs idle status is a CUT of the device topology graph; minimizing unsuppressed couplings is a maximum-cut problem — NP-complete in general. But device topologies are planar grids, and a classic duality holds: a cut's remaining-set corresponds to an ODD-VERTEX PAIRING in the planar dual graph. The scheduler finds small pairings via matching over odd-degree dual vertices plus top-k shortest-path relaxation, induces the cut, and constrains all gate-qubits to one side (dual edge deletion/re-insertion) — polynomial time, objective α·N_Q + N_C.
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Layer splitting and gate spreading new
When one layer cannot be well-suppressed, splitting it into two helps both metrics — fewer simultaneous gates means smaller regions and fewer unsuppressed couplings (in the worked example, one split leaves an entire layer with ZERO unsuppressed couplings). Two-qubit gates are additionally spread apart by a distance heuristic, since nearby simultaneous two-qubit gates are the worst offenders. The price is parallelism: execution time grows by under 2× — repaid many times over in fidelity.
The idea
Factor the problem along the driven/idle border. The whole-circuit unitary is exponentially expensive to optimize because it entangles every qubit’s evolution; the paper’s crucial observation is that crosstalk suppression does not need the whole unitary. Each border coupling has exactly one driven endpoint, and the pulse already being crafted for that qubit’s gate has enough freedom to cancel the coupling’s ZZ term as a side condition. Suppression thus LOCALIZES: optimize once per basic region (a gate and its surroundings, four qubits or fewer), reuse everywhere, compose freely. It is the same decomposition discipline this site’s cryogenic-decoder page used (all decisions local to a clique) and its GPU-forecasting page formalized (out-of-distribution wholes built from in-distribution parts) — locality as the antidote to exponential cost.
Idleness is not safety — and “nothing” can be an active operation. The counterintuitive core of the scheduling half: an idle qubit passively accumulates crosstalk on all its couplings, but a qubit executing an identity gate — pulses that implement no logical change — becomes a driven qubit whose pulses cancel the crosstalk around it. Doing nothing and actively doing nothing are physically different. The scheduler’s job becomes choosing where to spend identity pulses so that the unreachable (intra-region) couplings convert into reachable (cross-region) ones — and the elegant surprise is that this placement problem is exactly a graph cut, with the device’s planarity turning NP-complete max-cut into polynomial matching via the cut/odd-vertex-pairing duality. The reify-the-space lineage on this site gains a fifth formalism: poset, Steiner grid, CSP, MIP, and now planar duality.
Spend parallelism to buy fidelity — in this regime, the exchange rate is spectacular. Compiler orthodoxy maximizes parallelism to outrun decoherence. ZZ crosstalk inverts the gradient: simultaneous gates amplify each other’s errors, and splitting layers shrinks regions and unsuppressed-coupling counts. The measured trade — execution time under 2× longer for 11× average fidelity — echoes the fault-tolerance page’s stalling argument: when fidelity is the currency, modest slowdowns are cheap. And the decomposition of credit is honest: pulses contribute 43.7% of the improvement, scheduling 56.3%, and each alone underperforms the pair — co-optimization, again, as a measured quantity rather than a slogan.
One layer through the compiler
Three gates on a 5×3 grid, crosstalk everywhere
Region = connected component of same-status qubits. N_C = couplings with unsuppressed crosstalk; N_Q = qubits in the largest region. Numbers from the paper's worked example and evaluation.
Step 1 of 6
The layer lands; regions form
A CNOT on qubits 7-8 and Hadamards on 9 and 10 are scheduled together. The four driven qubits form one region; the eleven idle qubits form another. Nine couplings cross the border — and thirteen lie wholly inside the idle region, where no pulse acts.
the classification is the whole game: cross-region = fixable, intra-region = not status of every qubit ↔ a cut of the topology graph
Why it works
- Every cross-region coupling touches exactly one driven qubit → that gate’s pulses can cancel it as a side objective → suppression optimization localizes to ≤4-qubit basic regions whose solutions compose over arbitrary circuits, replacing exponential global optimization with a small offline library.
- Identity pulses convert qubit status without changing quantum state → intra-region couplings (unreachable) become cross-region (cancellable) → the scheduler can RESHAPE the border pulses defend, not just accept it.
- Driven/idle status is a cut of the planar device graph → cut remaining-sets are dual to odd-vertex pairings → the NP-complete coupling-minimization becomes polynomial matching plus shortest paths, with the α·N_Q + N_C objective pricing correlated-error size against coupling count.
- Simultaneous gates amplify each other’s crosstalk → splitting layers shrinks regions and unsuppressed counts → a sub-2× parallelism sacrifice purchases an 11× average fidelity gain — the right trade when fidelity is the scarce resource.
- Pulses and scheduling cover complementary coupling classes → neither alone suffices (43.7% / 56.3% credit split, each solo configuration inferior) → the co-optimization is the product, not either factor.
What it costs
- Parallelism, deliberately. Execution time grows by up to ~2×, lengthening exposure to decoherence; the paper shows the trade wins across T1/T2 sweeps, but devices where decoherence dominates crosstalk shift the balance.
- Residual intra-region crosstalk. Suppression is not total — the scheduler minimizes, not zeroes, N_C, and what remains inside regions persists; targets (N_Q below max degree, N_C below half the edges) are heuristic settings.
- Planarity and topology assumptions. The polynomial scheduling leans on planar device graphs (true of today’s grids and heavy-hex lattices); denser future connectivity would reopen the max-cut hardness.
- Pulse-library fidelity is load-bearing. The composed suppression is only as good as the basic-region optimizations; drive noise, leakage, and calibration drift (simulated and partially tested on hardware) erode the cancellation in practice.
- Scale of validation. Simulation reaches 12 qubits; the real-device demonstration is three qubits with Ramsey interferometry — convincing physics, but full-circuit hardware validation at scale remains open.
The evaluation
Density-matrix simulation across six benchmark families and four system sizes against the deployed compiler default (Gaussian pulses + parallelism-maximizing scheduling), with pulse-engine substitutions, solo-versus-co-optimization ablations, decoherence sweeps, tunable-coupler comparisons — and Ramsey experiments on real transmon hardware.
Three ways to fight an always-on interaction
| Property | Hardware redesign (tunable couplers / heterogeneous qubits / multi-path) | Global pulse optimization | Pulse + scheduling co-optimization |
|---|---|---|---|
| What changes | All pulses, jointly, against the whole-circuit unitary | ||
| Scalability | Scales in principle; cost and decoherence scale too | ||
| Device coverage | Excludes the simplest homogeneous fixed-coupling devices — which have the longest coherence | Any device, tiny circuits only | |
| Measured suppression | Strong where deployed (compared in simulation: co-optimization is competitive) | — | |
| Price paid | Coherence, fabrication, control lines | Compute that forecloses scale |
Check yourself
Check your understanding
1. A qubit with no gate scheduled on it seems safely out of the action. Predict why it is not — and how an identity gate, which changes no quantum state, protects it.
2. Global pulse optimization is exponential in qubit count, yet this paper optimizes pulses only on systems of at most ~4 qubits and claims whole-circuit suppression. What theorem-shaped fact makes the composition sound?
3. Choosing which idle qubits receive identity gates is NP-complete in general (max-cut). How does the scheduler solve it in polynomial time anyway?
4. The compiled circuits run up to ~2× SLOWER, directly opposing the maximize-parallelism orthodoxy of quantum compilers. Why is this trade correct here, and what result would falsify it?